El acceso a la memoria principal en los procesadores actuales supone un importante cuello de botella para las prestaciones, dado que los diferentes núcleos compiten por el limitado ancho de banda de memoria, agravando la brecha entre las prestaciones del procesador y las de la memoria principal. Distintas técnicas atacan este problema, siendo las más relevantes el uso de jerarquías de caché multinivel y la prebúsqueda. Las cachés jerárquicas aprovechan la localidad temporal y espacial que en general presentan los programas en el acceso a los datos, para mitigar las enormes latencias de acceso a memoria principal. Para limitar el número de accesos a la memoria DRAM, fuera del chip, los procesadores actuales cuentan con grandes cachés de último nivel (LLC). Para mejorar su utilización y reducir costes, estas cachés suelen compartirse entre todos los núcleos del procesador. Este enfoque mejora significativamente el rendimiento de la mayoría de las aplicaciones en comparación con el uso de cachés privados más pequeños. Compartir la caché, sin embargo, presenta una problema importante: la interferencia entre aplicaciones. La prebúsqueda, por otro lado, trae bloques de datos a las cachés antes de que el procesador los solicite, ocultando la latencia de memoria principal. Desafortunadamente, dado que la prebúsqueda es una técnica especulativa, si no tiene éxito puede contaminar la caché con bloques que no se usarán. Además, las prebúsquedas interfieren con los accesos a memoria normales, tanto los del núcleo que emite las prebúsquedas como los de los demás. Esta tesis se centra en reducir la interferencia entre aplicaciones, tanto en las caché compartidas como en el acceso a la memoria principal. Para reducir la interferencia entre aplicaciones en el acceso a la memoria principal, el mecanismo propuesto en esta disertación regula la agresividad de cada prebuscador, activando o desactivando selectivamente algunos de ellos, dependiendo de su rendimiento individual y de los requisitos de ancho de banda de memoria principal de los otros núcleos. Con respecto a la interferencia en cachés compartidos, esta tesis propone dos técnicas de particionado para la LLC, las cuales otorgan más espacio de caché a las aplicaciones que progresan más lentamente debido a la interferencia entre aplicaciones. La primera propuesta de particionado de caché requiere hardware específico no disponible en procesadores comerciales, por lo que se ha evaluado utilizando un entorno de simulación. La segunda propuesta de particionado de caché presenta una familia de políticas que superan las limitaciones en el número de particiones y en el número de vías de caché disponibles mediante la agrupación de aplicaciones en clústeres y la superposición de particiones de caché, por lo que varias aplicaciones comparten las mismas vías. Dado que se ha implementado utilizando los mecanismos para el particionado de la LLC que presentan algunos procesadores Intel modernos, esta propuesta ha sido evaluada en una máquina real. Los resultados experimentales muestran que el mecanismo de prebúsqueda selectiva propuesto en esta tesis reduce el número de solicitudes de memoria principal en un 20%, cosa que se traduce en mejoras en la equidad del sistema, el rendimiento y el consumo de energía. Por otro lado, con respecto a los esquemas de partición propuestos, en comparación con un sistema sin particiones, ambas propuestas reducen la iniquidad del sistema en un promedio de más del 25%, independientemente de la cantidad de aplicaciones en ejecución, y esta reducción en la injusticia no afecta negativamente al rendimiento. / Accessing main memory represents a major performance bottleneck in current processors, since the different cores compete among them for the limited offchip bandwidth, aggravating even more the so called memory wall. Several techniques have been applied to deal with the core-memory performance gap, with the most preeminent ones being prefetching and hierarchical caching. Hierarchical caches leverage the temporal and spacial locality of the accessed data, mitigating the huge main memory access latencies. To limit the number of accesses to the off-chip DRAM memory, current processors feature large Last Level Caches. These caches are shared between all the cores to improve the utilization of the cache space and reduce cost. This approach significantly improves the performance of most applications compared to using smaller private caches. Cache sharing, however, presents an important shortcoming: the interference between applications. Prefetching, on the other hand, brings data blocks to the caches before they are requested, hiding the main memory latency. Unfortunately, since prefetching is a speculative technique, inaccurate prefetches may pollute the cache with blocks that will not be used. In addition, the prefetches interfere with the regular memory requests, both the ones from the application running on the core that issued the prefetches and the others. This thesis focuses on reducing the inter-application interference, both in the shared cache and in the access to the main memory. To reduce the interapplication interference in the access to main memory, the proposed approach regulates the aggressiveness of each core prefetcher, and selectively activates or deactivates some of them, depending on their individual performance and the main memory bandwidth requirements of the other cores. With respect to interference in shared caches, this thesis proposes two LLC partitioning techniques that give more cache space to the applications that have their progress diminished due inter-application interferences. The first cache partitioning proposal requires dedicated hardware not available in commercial processors, so it has been evaluated using a simulation framework. The second proposal dealing with cache partitioning presents a family of partitioning policies that overcome the limitations in the number of partitions and the number of available ways by grouping applications and overlapping cache partitions, so multiple applications share the same ways. Since it has been implemented using the cache partitioning features of modern Intel processors it has been evaluated in a real machine. Experimental results show that the proposed selective prefetching mechanism reduces the number of main memory requests by 20%, which translates to improvements in unfairness, performance, and energy consumption. On the other hand, regarding the proposed partitioning schemes, compared to a system with no partitioning, both reduce unfairness more than 25% on average, regardless of the number of applications running in the multicore, and this reduction in unfairness does not negatively affect the performance. / L'accés a la memòria principal en els processadors actuals suposa un important coll d'ampolla per a les prestacions, ja que els diferents nuclis competeixen pel limitat ample de banda de memòria, agreujant la bretxa entre les prestacions del processador i les de la memòria principal. Diferents tècniques ataquen aquest problema, sent les més rellevants l'ús de jerarquies de memòria cau multinivell i la prebusca. Les memòries cau jeràrquiques aprofiten la localitat temporal i espacial que en general presenten els programes en l'accés a les dades per mitigar les enormes latències d'accés a memòria principal. Per limitar el nombre d'accessos a la memòria DRAM, fora del xip, els processadors actuals compten amb grans caus d'últim nivell (LLC). Per millorar la seva utilització i reduir costos, aquestes memòries cau solen compartir-se entre tots els nuclis del processador. Aquest enfocament millora significativament el rendiment de la majoria de les aplicacions en comparació amb l'ús de caus privades més menudes. Compartir la memòria cau, no obstant, presenta una problema important: la interferencia entre aplicacions. La prebusca, per altra banda, porta blocs de dades a les memòries cau abans que el processador els sol·licite, ocultant la latència de memòria principal. Desafortunadament, donat que la prebusca és una técnica especulativa, si no té èxit pot contaminar la memòria cau amb blocs que no fan falta. A més, les prebusques interfereixen amb els accessos normals a memòria, tant els del nucli que emet les prebusques com els dels altres. Aquesta tesi es centra en reduir la interferència entre aplicacions, tant en les cau compartides com en l'accés a la memòria principal. Per reduir la interferència entre aplicacions en l'accés a la memòria principal, el mecanismo proposat en aquesta dissertació regula l'agressivitat de cada prebuscador, activant o desactivant selectivament alguns d'ells, en funció del seu rendiment individual i dels requisits d'ample de banda de memòria principal dels altres nuclis. Pel que fa a la interferència en caus compartides, aquesta tesi proposa dues tècniques de particionat per a la LLC, les quals atorguen més espai de memòria cau a les aplicacions que progressen més lentament a causa de la interferència entre aplicacions. La primera proposta per al particionat de memòria cau requereix hardware específic no disponible en processadors comercials, per la qual cosa s'ha avaluat utilitzant un entorn de simulació. La segona proposta de particionat per a memòries cau presenta una família de polítiques que superen les limitacions en el nombre de particions i en el nombre de vies de memòria cau disponibles mitjan¿ cant l'agrupació d'aplicacions en clústers i la superposició de particions de memòria cau, de manera que diverses aplicacions comparteixen les mateixes vies. Atès que s'ha implementat utilitzant els mecanismes per al particionat de la LLC que ofereixen alguns processadors Intel moderns, aquesta proposta s'ha avaluat en una màquina real. Els resultats experimentals mostren que el mecanisme de prebusca selectiva proposat en aquesta tesi redueix el nombre de sol·licituds a la memòria principal en un 20%, cosa que es tradueix en millores en l'equitat del sistema, el rendiment i el consum d'energia. Per altra banda, pel que fa als esquemes de particiónat proposats, en comparació amb un sistema sense particions, ambdues propostes redueixen la iniquitat del sistema en més d'un 25% de mitjana, independentment de la quantitat d'aplicacions en execució, i aquesta reducció en la iniquitat no afecta negativament el rendiment. / Selfa Oliver, V. (2018). Adaptive Prefetching and Cache Partitioning for Multicore Processors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/112423 / TESIS

Les handovers sont des phénomènes inévitables dans les réseaux sans-fil mobiles. Lors du passage d'une station mobile d'un point d'accès à un autre, le handover affecte la qualité des transmissions, et ainsi, il est néfaste à la performance des réseaux sans-fil. De nombreuses techniques de réduction du délai lié au handover ont été proposées, mais la plupart ne sont pas adaptées aux attentes du nouveau type de réseau sans-fil mobile qu'est le réseau véhiculaire. Ce travail propose donc l'implémentation d'une méthode de réduction du délai encouru lors d'un handover dans les réseaux véhiculaires qui opèrent sous une technologie d'accès sans-fil adaptée pour les besoins des réseaux véhiculaires. Le travail est composé de deux blocs : le premier est l'implémentation d'IEEE 802.11p, qui est une variante de la norme générique d'IEEE 802.11 et qui est développée spécialement pour l'accès dans les réseaux véhiculaires, dans un simulateur de réseaux. L'autre partie concerne le choix d'une méthode de réduction du délai lié à l'étape de la recherche du handover. En tenant compte des réalités technologiques, le choix s'est porté sur une technique préconisant l'utilisation des cache pour contenir et diffuser de l'information sur les points d'accès avoisinants. La méthode proposée a été testée et a donné de très bons résultats réalistes. L'intégration des modules complémentaires pour refléter l'ensemble de la technique proposée au niveau du simulateur s'est aussi faite sans problèmes majeurs.

Hardware texture mapping is essential for real-time rendering. Unfortunately the memory bandwidth and latency often bounds performance in current graphics architectures. Bandwidth consumption can be reduced by compressing the texture map or by using a cache. However, the way a texture map occupies memory and how it is accessed affects the pattern of memory accesses, which in turn affects cache performance. Thus texture compression schemes and cache architectures must be designed in conjunction with each other. We define a sparse texture to be a texture where a substantial percentage of the texture is constant. Sparse textures are of interest as they occur often, and they are used as parts of more general texture compression schemes. We present a hardware compatible implementation of sparse textures based on B-tree indexing and explore cache designs for it. We demonstrate that it is possible to have the bandwidth consumption and miss rate due to the texture data alone scale with the area of the region of interest. We also show that the additional bandwidth consumption and hideable latency due to the B-tree indices are low. Furthermore, the caches necessary for these textures can be quite small.

Last Level Caches (LLCs) are critical to reducing processor stalls to off-chip memory and improving processing throughput, and replacement policy plays an important role in the performance of LLCs. Many replacement algorithms are designed to be thrash-resistant to protect the working set in the cache from scans, but a fundamental challenge is balancing thrash-resistance to changes to the working set over time as an application executes. In this thesis a novel Set-Associative History-Aided Adaptive Replacement Cache (SHARC) LLC replacement algorithm is proposed, which adjusts scan-resistance at run-time based on the current memory access properties of the application. This policy segregates the cache to protect the working set from scans and utilizes history information from recently evicted cache lines to increase or decrease amount of cache reserved for the working set. On average, SHARC improves IPC by approximately 11% over LRU replacement policy while only requiring 14% increase in overhead. The SHARC-NRU replacement policy is also proposed to reduce this overhead and achieves approximately 10% performance improvement and requires 11% less overhead than LRU.

Com a grande quantidade de informações existentes nas aplicações computacionais hoje em dia, cada vez mais tornam-se necessários mecanismos que facilitem e aumentem o desempenho da recuperação dessas informações. Nesse contexto vem surgindo os bancos de dados chamados de NOSQL, que são bancos de dados tipicamente não relacionais que, em prol da disponibilidade e do desempenho em ambientes com enormes quantidades de dados, abrem mão de requisitos antes vistos como fundamentais. Neste trabalho iremos lidar com esse cenário ao implementar o módulo de consultas distribuídas do JBoss Infinispan, um sistema de cache distribuído que funciona também como um banco de dados NOSQL em memória. Além de apresentar a implementação desse módulo, iremos falar do surgimento do movimento NOSQL, de como se caracterizam esses bancos e de onde o Infinispan se insere nesse movimento. / With the big amount of data available to computer applications nowadays, there is an increasing need for mechanisms that facilitate the retrieval of such data and improve data access performance. In this context we see the emergence of so-called NOSQL databases, which are databases that are typically non-relational and that give up fulfilling some requirements previously seen as fundamental in order to achieve better availability and performance in big data environments. In this work we deal with the scenario above and implement a module that supports distributed queries in JBoss Infinispan, a distributed cache system that works also as an in-memory NOSQL database. Besides presenting the implementation of that module, we discuss the emergence of the NOSQL movement, the characterization of NOSQL databases, and where Infinispan fits in this context.

by Yung, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 107-110). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Cache --- p.1 / Chapter 1.1.1 --- Introduction --- p.1 / Chapter 1.1.2 --- Data Prefetching --- p.2 / Chapter 1.2 --- Register --- p.2 / Chapter 1.3 --- Problems and Challenges --- p.3 / Chapter 1.3.1 --- Overhead of registers --- p.3 / Chapter 1.3.2 --- EReg --- p.5 / Chapter 1.4 --- Organization of the Thesis --- p.6 / Chapter 2 --- Previous Studies --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Data aliasing --- p.9 / Chapter 2.3 --- Data prefetching --- p.12 / Chapter 2.3.1 --- Introduction --- p.12 / Chapter 2.3.2 --- Hardware Prefetching --- p.12 / Chapter 2.3.3 --- Prefetching with Software Support --- p.13 / Chapter 2.3.4 --- Reducing Cache Pollution --- p.14 / Chapter 3 --- BASIC and ADM Models --- p.15 / Chapter 3.1 --- Introduction of Basic Model --- p.15 / Chapter 3.2 --- Architectural and Operational Detail of Basic Model --- p.18 / Chapter 3.3 --- Discussion --- p.19 / Chapter 3.3.1 --- Implicit Storing --- p.19 / Chapter 3.3.2 --- Associative Logic --- p.22 / Chapter 3.4 --- Example for Basic Model --- p.22 / Chapter 3.5 --- Simulation Results --- p.23 / Chapter 3.6 --- Temporary Storage Problem in Basic Model --- p.29 / Chapter 3.6.1 --- Introduction --- p.29 / Chapter 3.6.2 --- Discussion on the Solutions --- p.31 / Chapter 3.7 --- Introduction of ADM Model --- p.35 / Chapter 3.8 --- Architectural and Operational Detail of ADM Model --- p.37 / Chapter 3.9 --- Discussion --- p.39 / Chapter 3.9.1 --- File Partition --- p.39 / Chapter 3.9.2 --- STORE Instruction --- p.39 / Chapter 3.10 --- Example for ADM Model --- p.40 / Chapter 3.11 --- Simulation Results --- p.40 / Chapter 3.12 --- Temporary storage Problem of ADM Model --- p.46 / Chapter 3.12.1 --- Introduction --- p.46 / Chapter 3.12.2 --- Discussion on the Solutions --- p.46 / Chapter 4 --- ADS Model and ADSM Model --- p.49 / Chapter 4.1 --- Introduction of ADS Model --- p.49 / Chapter 4.2 --- Architectural and Operational Detail of ADS Model --- p.50 / Chapter 4.3 --- Discussion --- p.52 / Chapter 4.3.1 --- Prefetching Priority --- p.52 / Chapter 4.3.2 --- Data Prefetching --- p.53 / Chapter 4.3.3 --- EReg File Splitting --- p.53 / Chapter 4.3.4 --- Compiling Procedure --- p.53 / Chapter 4.4 --- Example for ADS Model --- p.54 / Chapter 4.5 --- Simulation Results --- p.55 / Chapter 4.6 --- Discussion on the Architectural and Operational Variations for ADS Model --- p.62 / Chapter 4.6.1 --- Temporary storage Problem --- p.62 / Chapter 4.6.2 --- Operational variation for Data Prefetching --- p.63 / Chapter 4.7 --- Introduction of ADSM Model --- p.64 / Chapter 4.8 --- Architectural and Operational Detail of ADSM Model --- p.65 / Chapter 4.9 --- Discussion --- p.67 / Chapter 4.10 --- Example for ADSM Model --- p.67 / Chapter 4.11 --- Simulation Results --- p.68 / Chapter 4.12 --- Discussion on the Architectural and Operational Variations for ADSM Model --- p.71 / Chapter 4.12.1 --- Temporary storage Problem --- p.71 / Chapter 4.12.2 --- Operational variation for Data Prefetching --- p.73 / Chapter 5 --- IADSM Model and IADSMC&IDLC Model --- p.75 / Chapter 5.1 --- Introduction of IADSM Model --- p.75 / Chapter 5.2 --- Architectural and Operational Detail of IADSM Model --- p.76 / Chapter 5.3 --- Discussion --- p.79 / Chapter 5.3.1 --- Implicit Loading --- p.79 / Chapter 5.3.2 --- Compiling Procedure --- p.81 / Chapter 5.4 --- Example for IADSM Model --- p.81 / Chapter 5.5 --- Simulation Results --- p.84 / Chapter 5.6 --- Temporary Storage Problem of IADSM Model --- p.87 / Chapter 5.7 --- Introduction of IADSMC&IDLC Model..........: --- p.88 / Chapter 5.8 --- Architectural and Operational Detail of IADSMC & IDLC Model --- p.89 / Chapter 5.9 --- Discussion --- p.90 / Chapter 5.9.1 --- Additional Operations --- p.90 / Chapter 5.9.2 --- Compiling Procedure --- p.93 / Chapter 5.10 --- Example for IADSMC&IDLC Model --- p.93 / Chapter 5.11 --- Simulation Results --- p.94 / Chapter 5.12 --- Temporary Storage Problem of IADSMC&IDLC Model --- p.96 / Chapter 6 --- Compiler and Memory System Support for EReg --- p.99 / Chapter 6.1 --- Impact on Compiler --- p.99 / Chapter 6.1.1 --- Register Usage --- p.99 / Chapter 6.1.2 --- Effect of Unrolling --- p.100 / Chapter 6.1.3 --- Code Scheduling Algorithm --- p.101 / Chapter 6.2 --- Impact on Memory System --- p.102 / Chapter 6.2.1 --- Memory Bottleneck --- p.102 / Chapter 6.2.2 --- Size of EReg Files --- p.103 / Chapter 7 --- Conclusions --- p.104 / Chapter 7.1 --- Summary --- p.104 / Chapter 7.2 --- Future Research --- p.105 / Bibliography --- p.107 / Chapter A --- Source code of the Kernels --- p.111 / Chapter B --- Program Analysis --- p.126 / Chapter B.1 --- Program analysed by Basic Model --- p.126 / Chapter B.2 --- Program analysed by ADM Model --- p.133 / Chapter B.3 --- Program analysed by ADS Model --- p.140 / Chapter B.4 --- Program analysed by ADSM Model --- p.148 / Chapter B.5 --- Program analysed by IADSM Model --- p.156 / Chapter B.6 --- Program analysed by IADSMC&IDLC Model --- p.163 / Chapter C --- Cache Simulation on Prefetching of ADS model --- p.174

In the last decade, multi-threaded systems and resource sharing have brought a number of technologies that facilitate our daily tasks in a way we never imagined. Among others, cloud computing has emerged to offer us powerful computational resources without having to physically acquire and install them, while smartphones have almost acquired the same importance desktop computers had a decade ago. This has only been possible thanks to the ever evolving performance optimization improvements made to modern microarchitectures that efficiently manage concurrent usage of hardware resources. One of the aforementioned optimizations is the usage of shared Last Level Caches (LLCs) to balance different CPU core loads and to maintain coherency between shared memory blocks utilized by different cores. The latter for instance has enabled concurrent execution of several processes in low RAM devices such as smartphones. Although efficient hardware resource sharing has become the de-facto model for several modern technologies, it also poses a major concern with respect to security. Some of the concurrently executed co-resident processes might in fact be malicious and try to take advantage of hardware proximity. New technologies usually claim to be secure by implementing sandboxing techniques and executing processes in isolated software environments, called Virtual Machines (VMs). However, the design of these isolated environments aims at preventing pure software- based attacks and usually does not consider hardware leakages. In fact, the malicious utilization of hardware resources as covert channels might have severe consequences to the privacy of the customers. Our work demonstrates that malicious customers of such technologies can utilize the LLC as the covert channel to obtain sensitive information from a co-resident victim. We show that the LLC is an attractive resource to be targeted by attackers, as it offers high resolution and, unlike previous microarchitectural attacks, does not require core-colocation. Particularly concerning are the cases in which cryptography is compromised, as it is the main component of every security solution. In this sense, the presented work does not only introduce three attack variants that can be applicable in different scenarios, but also demonstrates the ability to recover cryptographic keys (e.g. AES and RSA) and TLS session messages across VMs, bypassing sandboxing techniques. Finally, two countermeasures to prevent microarchitectural attacks in general and LLC attacks in particular from retrieving fine- grain information are presented. Unlike previously proposed countermeasures, ours do not add permanent overheads in the system but can be utilized as preemptive defenses. The first identifies leakages in cryptographic software that can potentially lead to key extraction, and thus, can be utilized by cryptographic code designers to ensure the sanity of their libraries before deployment. The second detects microarchitectural attacks embedded into innocent-looking binaries, preventing them from being posted in official application repositories that usually have the full trust of the customer.

by Hon-Kai, Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 102-105). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Scheduling In Real-time Systems --- p.4 / Chapter 1.3 --- Cache Memories --- p.5 / Chapter 1.4 --- Outline Of The Dissertation --- p.8 / Chapter 2 --- Related Work --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- Predictable Cache Designs --- p.9 / Chapter 2.2.1 --- Locking Cache Lines Design --- p.9 / Chapter 2.2.2 --- Partially Dynamic And Static Cache Partition Allocation Design --- p.10 / Chapter 2.2.3 --- SMART (Strategic Memory Allocation for Real Time) Cache Design --- p.10 / Chapter 2.3 --- Prefetching --- p.11 / Chapter 2.3.1 --- Introduction --- p.11 / Chapter 2.3.2 --- Hardware Support Prefetching --- p.12 / Chapter 2.3.3 --- Software Assisted Prefetching --- p.12 / Chapter 2.3.4 --- Partial Cache Hit --- p.13 / Chapter 2.3.5 --- Cache Pollution Problems --- p.13 / Chapter 2.4 --- Cache Line Replacement Policies --- p.13 / Chapter 2.5 --- Main Memory Update Policies --- p.14 / Chapter 2.6 --- Summaries --- p.15 / Chapter 3 --- Problems And Motivations --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Problems --- p.16 / Chapter 3.2.1 --- Modern Cache Architecture Is Inappropriate For Real-time Systems --- p.16 / Chapter 3.2.2 --- Intertask Interference: The Effects Of Preemption --- p.17 / Chapter 3.2.3 --- Intratask Interference: Cache Line Collision --- p.20 / Chapter 3.3 --- Motivations --- p.21 / Chapter 3.3.1 --- Improvement Of The Cache Performance In Real-time Systems --- p.21 / Chapter 3.3.2 --- Hiding of Preemption Effects --- p.22 / Chapter 3.4 --- Conclusions --- p.25 / Chapter 4 --- Proposed Real-Time Cache Design --- p.26 / Chapter 4.1 --- Introduction --- p.26 / Chapter 4.2 --- Concepts Definition --- p.26 / Chapter 4.2.1 --- Tasks Definition --- p.26 / Chapter 4.2.2 --- Cache Performance Values --- p.27 / Chapter 4.3 --- Issues Related To Proposed Real-Time Cache Design --- p.28 / Chapter 4.3.1 --- A Task Serving Policy --- p.30 / Chapter 4.3.2 --- Number Of Private And Shared Cache Partitions --- p.31 / Chapter 4.3.3 --- Controlling The Cache Partitions: Cache Partition Table And Pro- cess Info Table --- p.32 / Chapter 4.3.4 --- Re-organization Of Task Owns Cache Partition(s) --- p.34 / Chapter 4.3.5 --- Handling The Bus Bandwidth: Memory Requests Queue ( MRQ ) --- p.35 / Chapter 4.3.6 --- How To Address The Cache Models --- p.37 / Chapter 4.3.7 --- Data Coherence Problems For Partitioned Cache Model And Non- partitioned Cache Model --- p.39 / Chapter 4.4 --- Mechanism For Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.1 --- Basic Operation Of Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.2 --- Assumptions And Rules --- p.43 / Chapter 4.4.3 --- First Round Dynamic Cache Partition Re-allocation --- p.44 / Chapter 4.4.4 --- Later Round Dynamic Cache Partition Re-allocation --- p.45 / Chapter 5 --- Simulation Environments --- p.56 / Chapter 5.1 --- Proposed Architectural Model --- p.56 / Chapter 5.2 --- Working Environment For Proposed Real-time Cache Models --- p.57 / Chapter 5.2.1 --- Cost Model --- p.57 / Chapter 5.2.2 --- System Model --- p.64 / Chapter 5.2.3 --- Fair Comparsion Between The Unified Cache And The Separate Caches --- p.64 / Chapter 5.2.4 --- Operations Within The Preemption --- p.65 / Chapter 5.3 --- Benchmark Programs --- p.65 / Chapter 5.3.1 --- The NASA7 Benchmark --- p.66 / Chapter 5.3.2 --- The SU2COR Benchmark --- p.66 / Chapter 5.3.3 --- The TOMCATV Benchmark --- p.66 / Chapter 5.3.4 --- The WAVE5 Benchmark --- p.67 / Chapter 5.3.5 --- The COMPRESS Benchmark --- p.67 / Chapter 5.3.6 --- The ESPRESSO Benchmark --- p.68 / Chapter 5.4 --- Simulations Parameters --- p.68 / Chapter 6 --- Analysis Of Simulations --- p.71 / Chapter 6.1 --- Introduction --- p.71 / Chapter 6.2 --- Trace Files Statistics --- p.71 / Chapter 6.3 --- Interpretation Of Partial Cache Hit --- p.72 / Chapter 6.4 --- The Effects Of Cache Size --- p.72 / Chapter 6.4.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.72 / Chapter 6.5 --- The Effects Of Cache Partition Size --- p.76 / Chapter 6.5.1 --- Performance Of Model 3 --- p.79 / Chapter 6.5.2 --- Performance Of Model 1 --- p.79 / Chapter 6.6 --- The Effects Of Line Size --- p.80 / Chapter 6.6.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.80 / Chapter 6.7 --- The Effects Of Set Associativity --- p.83 / Chapter 6.7.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.83 / Chapter 6.8 --- The Effects Of The Best-expected Cache Performance --- p.84 / Chapter 6.8.1 --- Performance of Model 1 --- p.87 / Chapter 6.8.2 --- Performance of Model 3 --- p.88 / Chapter 6.9 --- The Effects Of The Standard-expected Cache Performance --- p.89 / Chapter 6.9.1 --- Performance Of Model 1 --- p.89 / Chapter 6.9.2 --- Performance Of Model 3 --- p.91 / Chapter 6.10 --- The Effects Of Cycle Execution Time/Cycle Deadline Period --- p.92 / Chapter 6.10.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.92 / Chapter 7 --- Conclusions And Future Work --- p.95 / Chapter 7.1 --- Conclusions --- p.95 / Chapter 7.1.1 --- Unified Cache Model Is More Suitable In Real-time Systems --- p.99 / Chapter 7.1.2 --- Comments On Aperiodic Tasks --- p.100 / Chapter 7.2 --- Future Work --- p.100

The radiation climate of Cache Valley was established f rom the continuous recordings of global and diffuse sky radiation at Utah State University campus from June 1968 to July 1969 and August 1968 to July 1969, respectively. The influence of topographic features during summer and winter conditions a t seven representative locations running on an east-west direction across the valley were determined by making short term measurements on clear days. A comparison of the clear day average global radiation on approximate dates of the same solar declination shows higher values during late winter and spring than t he values during late summer and autumn. This is mainly the influence of the higher atmospheric water vapor during the warmer months. An interesting fact is, that not only the direct , but also the scattered radiation shows higher values during the spring months . This is caused by additional reflection from the snow-covered mountain slopes . In the curve showing the distribution of the diffuse sky radiation on completely cloudy days, the effect of the multiple reflection between the ground surface and t he bases of clouds is very prominent in the period when there is snow on the ground. sky radiation at Utah State University campus and to study the local influences of local topography on the receipt of global and diffuse sky radiation at various locations across the valley on an east-west direction by making short term measurements under summer and winter conditions . In a mountain valley like Cache Valley, the difference in climate between the two opposite sides can largely be attributed to differences in the amounts of radiation received. This study was conducted on a scale where the incoming solar radiation may be influenced by topographic features.

Economic development that increases per capita income and creates additional jobs through expansion of present businesses and/or introduction of new businesses and business income is the goal of planners in Cache, Rich , and Box Elder Counties . To help with this goal a Northern Utah study group was organized to gather data on quality, quantity, and use of human, social, physical, and economic resources. This thesis is part of the main study and only includes Cache County. Input- output models are effective predicting tools. These tools are used in this analysis . To predict different output changes in the economy, final demand was adjusted four basic ways in the 1967 model. University and student spending were removed from final demand. For projections to 1980 final demand was increased by expanding university and student spending. Student spending was increased with university and other spending held constant. Another change was calculated to predict potential influence by changing final demand in each sector one percent one sector at a time. Results indicate that for economic development, input-output analysis can be used. If demand could be increased, Utah State University could be an effective area to develop since it affects all 32 sectors producing in the county. No other industry or sector affects as many other sectors . In the model, if student population were increased 17 percent, business income in 1967 would have been increased by $2,162,000. If the university and the students were removed from the model in 1967 , business income would have decreased by an amount greater than $15 ,000,000. If the university spending increased 49 percent and student population increased 70 percent (projections to 1980) , business income would increase at least $10 , 000,000.