This work presents a high performance digital controller of a single phase PWM sinusoidal inverter, using a 16-bits fixed point DSP. This converter is typically used in UPS (Uninterruptible Power Supplies), where a sinusoidal output voltage is desired. The digital controller has an internal filter capacitor current loop, and an external output voltage loop. Experimental results showing the performance of the system under linear and non-linear loads are presented, where a low total harmonic distortion (THD) is achieved. / Este trabalho apresenta um controlador digital de alto desempenho para um inversor PWM senoidal monofásico, usando um processador digital de sinais de 16 bits, ponto fixo. Esta topologia é tipicamente utilizada em sistemas UPS ( Uninterruptible Power Supplies ), onde uma tensão de saída senoidal é desejada. O controlador digital proposto consiste numa malha interna de realimentação da corrente do capacitor do filtro de saída, uma malha externa de realimentação da tensão de saída. Resultados experimentais mostrando o desempenho do sistema para cargas lineares e não-lineares são apresentados, onde uma baixa distorção harmônica total (THD) é observada, e é demonstrada uma elevada rigidez dinâmica da tensão de saída para transientes de carga. / Mestre em Ciências

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.