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Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal CalibrationLindeberg, Johan January 2014 (has links)
The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In the complete measurement unit, in which the ADC is part of, different sensors will be measured. One set of these sensors are three strain gauges with weak output signals which are to be pre-amplified before being converted. The focus of the application for the ADC has been these sensors as they were considered a limiting factor. The report describes theory for the algorithmic and incremental converter as well as a hybrid converter utilizing both of the two converter structures. All converters are based on one operational amplifier and they operate in repetitive fashions to obtain power efficient designs on a small chip area although at low conversion rates. Two converters have been designed and implemented to different degrees of completeness. One is a 13 bit algorithmic (or cyclic) converter which uses a switching scheme to reduce the problem of capacitor mismatch. This converter was implemented at transistor level and evaluated separately and to some extent also with sub-components. The second converter is a hybrid converter using both the operation of the algorithmic and incremental converter to obtain 16 bits of resolution while still having a fairly high sample rate.
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Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor NodesOmran, Hesham 11 1900 (has links)
Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants,
and wearable devices. The energy consumption of the sensor node needs to
be minimized to avoid battery replacement, or even better, to enable the device to
survive on energy harvested from the ambient. Capacitive sensors do not consume
static power; thus, they are attractive from an energy efficiency perspective. In addition,
they can be employed in a wide range of sensing applications. However, the
sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the
dominant source of energy consumption in the system. Thus, the development of
energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive
sensor nodes.
In the first part of this dissertation, we propose several energy-efficient CDC architectures
for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine
multislope CDC that employs both current and frequency scaling to achieve
significant improvement in energy efficiency. Second, we analyze the limitations of
successive approximation (SAR) CDC, and we address these limitations by proposing
a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an
inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM)
of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent
energy efficiency for a scalable sample rate.
In the second part of this dissertation, we study the matching properties of small
integrated capacitors, which are an integral component of energy-efficient CDCs. Despite
conventional wisdom, we experimentally illustrate that the mismatch of small
capacitors can be directly measured, and we report mismatch measurements for subfemtofarad
integrated capacitors. We also correct the common misconception that
lateral capacitors match better than vertical capacitors, and we identify the conditions
that make one implementation preferable.
In the third and last part of this dissertation, we investigate the potential of novel
metal-organic framework (MOF) thin films in capacitive gas sensing. We provide
sensitivity-based optimization and simple fabrication flow for capacitive interdigitated
electrodes. We use a custom flexible gas sensor test setup that is designed and built
in-house to characterize MOF-based capacitive gas sensors.
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