With the emergence of quantum physics and computer science in the 20th century, a new era was born which can solve very difficult problems in a much faster rate or problems that classical computing just can't solve. In the 21st century, quantum computing needs to be used to solve tough problems in engineering, business, medical, and other fields that required results not today but yesterday. To make this dream come true, engineers in the semiconductor industry need to make the quantum circuits a reality. To realize quantum circuits and make them scalable, they need to be fault tolerant, therefore Clifford+T gates need to be implemented into those circuits. But the main issue is that in the Clifford+T gate set, T gates are expensive to implement. Carry Look-Ahead addition circuits have caught the interest of researchers because the number of gate layers encountered by a given qubit in the circuit (or the circuit's depth) is logarithmic in terms of the input size n. Therefore, this thesis focuses on optimizing previous designs of out-of-place and in-place Carry Look-Ahead Adders to decrease the T-count, sum of all T and T Hermitian transpose gates in a quantum circuit.

This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers. A high speed and low power 8-bit CLA using dual- Vth domino logic blocks arranged in a PLA-like style with pipelining is presented. According to parallely precharge and sequentially evaluate in a cascaded set of domino logic blocks, transistors in the precharge part and the evaluation part of dual- Vth domino logic are, respectively, replaced by high Vth transistors to reduce subthreshold leakage current through OFF transistors, and low Vth transistors. Moreover, an nMOS transistor is inserted in the precharge phase of the output inverter such that the two-phase dual- Vth domino logic can be properly applied in a pipeline structure. Consequently, the proposed design keeps the advantage of high speed while attaining the effect of low power dissipation. A low-cost digital I/Q separator is presented in the second part of this thesis. Using digital I/Q separator in place of the traditional analog I/Q separator guarantees the design conquer gain and phase mismatch problems between the I and Q channels. The proposed design can berealized by inverters and shifters such that the goal of low cost can be achieved.

<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>

Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.