In contemporary communication systems, Digital-to-Analog Converters (DAC), Signal Defined Radio (SDR) signal creation, and clock data recovery are essential components. DACs convert digital signals to analog signals, creating continuous waveforms. DACs provide versatility in the transmission of SDR by supporting a range of communication protocols. Clock data recovery enables precise signal recovery and synchronization at the receiver end. These elements work together to provide effective and high-quality communication systems across several sectors. With the development of quantum computing, these SDR systems also find extensive use in generating precisely timed signals for controlling components of a quantum computer and also for read-out operations from various specialized instruments. This thesis demonstrates an FPGA (Xilinx vcu118) with a DAC (Analog Devices AD9081) platform. It employs SDR for generating of periodic signals and also stream of bits which are then recovered using a simple Clock Data Recovery technique. The signal integrity of the generated signals and error-rate from the proposed Clock Data Recovery technique is also analyzed. / Master of Science / Communication systems in our networked world depend on key technologies to provide dependable connectivity. By converting digital data into continuous waveforms, Digital-to- Analog Converters (DACs) serve a crucial role in enabling the generation of various analog signals. This makes it possible for Software-Defined Radio (SDR) to produce a variety of modulated signals and enables smooth communication between various hardware and software systems. The Clock and Data Recovery (CDR) algorithms correct for clock fluctuations and phase offsets to provide precise signal recovery and synchronization. Together, these technologies improve communication networks' effectiveness and dependability, allowing seamless connectivity and enhancing our networked experiences. This thesis presents an SDR platform comprising Xilinx FPGA vcu118 and Analog Devices high-speed DAC/ADC AD9081. A CDR algorithm is also proposed to recover data from the signals generated by the DAC, and its effectiveness and error rate is also analyzed.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.