A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.

Model-driven software development can help tackle complexity when developing large software systems. Model-driven development tools facilitate this. Such tools support multiple features and languages; some are multi-platform and support multi-language code generation from models. Umple is a full-featured open source language and modelling tool that we used as a basis for this thesis. Distribution concerns have become a critical part of modern software systems. In this thesis, we present how we extended Umple to support the development of model-driven synchronous or asynchronous distributed systems. Our contributions provide simple syntax, model analysis capabilities, and programming APIs, which allow users to change the configuration of systems both at development and deployment stages. We also demonstrate how a system can be modeled without distribution concerns and easily be transformed to a distributed system through our approach. The contributions of this thesis are: a) Creating a mechanism to distribute objects in Umple; b) Developing new semantics for modelling of distributed objects and providing supporting syntax for this in Umple; c) Investigating different patterns and technologies to implement code generation for distributed systems; d) Implementation, testing, and comparison of the distributed feature in Umple for executable Java code; and e) implementing a mechanism to dynamically modify the distribution plan at runtime.

This thesis deals with the design and implementation of Android application development tool based on model driven software development. The first part of the thesis is focused on general software development and next part on software development based on model driven development and executable UML. In next part Android platform, methods of Android application development and existing MDD tools are described. This thesis continues with the design of my own MDD tool for the creation of Android applications. The designed tool is realized like Gradle plugin and independent development environment using thisplugin. The designed tool is based on fUML and ALF language. The features and options of development tool are demonstrated by creation of example application.

The diploma thesis deals with an automatic code generation for PLC from Siemens. The first part focuses on currently available tools for code generation and options of C# library Siemens TIA Openness. Furthermore, a design for the project structure in the TIA portal is created. Finally, a user application for automatic code generation in TIA portal v15 is designed and created, especially suitable for larger projects that could be divided into individual stations.

This thesis describes opinions about generating code from PNtalk language into more standard object orinted languages, such as C++ or Java. Goal is to construct model of the formalism of Object Oriented Petri Nets (OOPN), represented in PNtalk languege in mentioned languages. This model should be simlpier and more effective than actual implementation in Smalltalk language. Thesis also contains ideas about abstactization the code generator to be able to generate code in various languages.

This thesis describes code generation using design patterns. It deals with questions of specification of design patterns and their usage in code generation. The main part of thesis follows describtions of design patterns, their categorization, usage purpose and main ways of design patterns definitions. It describes the most often used formal design patterns specifications, their possible usage in code generation and design of algorithm for searching similar structures of patterns in source code in detail.

Der Große Beleg dokumentiert die Entwicklung eines Java Code-Generators für Dresden OCL2 for Eclipse. Schwerpunkt der Arbeit liegt dabei auf der Abbildung der Object Constraint Language auf die Programmiersprache Java mit Hilfe von AspectJ.

The industrial manufacturing of today is achieved through the use of programmable logic controllers (PLC). The way PLCs are programmed remains largely unchanged since their conception 40 years ago, but complexity and software size have increased, and requirements have becomemore elaborate. Model-driven engineering (MDE) practices, formal verification and automated testing could help manage these challenges. This study seeks to improve development practices in the context of a company that delivers automation projects. Through design science methodology the state of the field is investigated and an artefact is developed. The artefact shows potential benefits resulting from the introduction of model-driven code generation, which is evaluated through an experiment with engineers. Our results indicate the engineers may benefit from incorporating generated code in their work.

Researchers use datasets of Question-Solution pairs to train machine learning models, such as source code generation models. A Question-Solution pair contains two parts: a programming question and its corresponding Solution Snippet. A Solution Snippet is a source code that solves a programming question. These datasets of Question-Solution pairs can be extracted from a number of different platforms. In this research, I study how Question-Solution pairs are extracted from Stack Overflow (SO). There are two limitations of datasets of Question-Solution pairs extracted from SO: (1) according to the authors of these datasets, some Question-Solution pairs contain Solution Snippets that do not solve the question correctly, and (2) these datasets do not contain the information on how Solution Snippets need to be reused, and such information would enhance the reusability of Solution Snippets. These limitations of datasets of pairs could adversely affect the quality of the code being generated by machine learning models. In this research, I conducted a qualitative study to categorize various presentations of Solution Snippets in SO’s answers as well as how Solution Snippets can be adapted for reuse. By doing so, I identified eight categories of how Solution Snippets are presented in SO’s answers and five categories of how Solution Snippets could be adapted. Based on these results, I concluded several potential reasons why it is not easy to create datasets of Question-Solution pairs. The first categorization informs that finding the correct location of the Solution Snippet is challenging when there are several code blocks within the answer to the question. Subsequently, the researcher must identify which code within that code block is the Solution Snippet. The second categorization informs that most Solution Snippets appear challenging to be adapted for reuse, and how Solution Snippets are potentially adapted is not explicitly stated in them. These insights shed light on creating better quality datasets from questions and answers posted on Stack Overflow. / Graduate

Mathematical optimization has many applications in operations research, image processing, and machine learning, demanding not only computational efficiency but also convenience and correctness in constructing complex models. In this work, we introduce HashedExpression, an open-source algebraic modeling lan- guage (AML) that allows users to express unconstrained, box-constrained, and scalar-expressions-constrained optimization problems, aimed at embeddability, type-safety, and high-performance through symbolic transformation and code generation. Written in Haskell, a statically-typed, purely functional program- ming language, HashedExpression places a great emphasis on modeling correct- ness by providing users with a type-safe, correct-by-construction interface that uses Haskell type-level programming to express constraints on correctness which the compiler uses to flag many modelling errors as type errors (at compile time). We show how type-safety can be added in steps, first matching expressions’ shape and then associated physical units. The library implements symbolic ex- pressions with a hashed indexing scheme to implement common subexpression elimination (CSE). It abstracts away details of the underlying lookup table via monadic type class instances. We explain how using symbolic expressions with CSE enables performance-enhance transformations and automatic computation of derivatives without the issue of “expression swelling”. For high-performance purposes, we generate low-level C/C++ code for symbolic expressions and pro- vide bindings to open-source optimization solvers such as Ipopt or L-BFGS-B. We explain how this architecture lays the groundwork for future work on par- allelization including SIMDization and targetting multi-core CPUs and GPUs, and other hardware acceleration. / Thesis / Master of Science (MSc)