<p>Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning.</p><p>This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.</p>

Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning. This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

The main focus in this diploma thesis is to analyse ARM microcontroller ATSAM3X8E, audio codec TLV320DAC3203 and CAN / RS485 bus for communication possibly used in device design. This device's purpose is to establish communicatio between elevator cabin and central control unit. Finally, there is design made for this communication device and measurement of CAN bus speed on H05VVH6 cable.

The topic of the master's thesis is about transmission of multimedia via network with help of compression’s algorithm used in codec MPEG-4 part 10 and Real Time Protocol (RTP). First part of this master thesis will be familiarization with basic terms about multimedia. It will be queried about techniques of compression axioms for audio and video, justification for necessary use of compression in transmitting multimedia via network. Also, here will be subscribed principles and properties of Real Time Protocol, which was designed for multimedia stream. From the start, competent codec for implementation of two applications (client, server) with read raw video and audio data, will choose the following : compression with help of codec Theora (Vorbis), transfer via network in RTP packets, decode and play at visual form for end user. Complete subscription of implementation for both applications written in programming languages C/C++ and Java, will be certain. The basic overview about this problematic experience with implementation, which were here concluded, are the reasons for reading this master thesis.

This thesis is focused on the design of secured audio codec for Asterisk PBX. The first chapter is focused on the basic division of traditional PBX producers and the open source PBX. The second chapter explains the structure of Asterisk PBX and its fundamental difference from a traditional PBX. Asterisk is based on components called modules, therefore the work also deals with the most important modules for operation of exchanges and their division of terms of support and dividing by the type of application and their properties. In this chapter there are described in more detail audio codec A-law and u-law. The third chapter contains simple instructions to get your orientation in the construction of the module for Asterisk PBX and this guide is accompanied by a simple example of creating a module demonstration of his method of translation, commissioning and loaded into Asterisk. Simulation of voice security is in the fourth chapter which provides a description of the proposed security solutions with subsequent implementation in Simulink. This simulation verifies the functionality of the solution proposed security phone call. In the fifth chapter outlines the historical use of encryption techniques primarily mirroring the spectrum and time division signal and comparing them with current modern digital technics. In the last sixth chapter is the actual implementation audio codec module with encryption.

Diploma thesis focuses on the selection of suitable HW solution for parallell processing of multiple audio sources. Compares several different platforms based on architectures ARM, x86 and Epiphany, compares their performance in serial and parallel data processing, their energy consumption and price.

This thesis deals with the issues of detecting the codec used for the encoding of voice data carried by the RTP protocol without having access to the information carried by signalisation protocols in VoIP applications. Its main goal is to create and implement a fast algorithm for detecting the codec used for voice transfer via the RTP protocol. This algorithm should be fast enough to be used for offline analysis of captured data as well as for real-time online analysis. For research of possibilities were compared two approaches of detection. Detection by the characteristics of the codecs was chosen to solve the problem itself. Within the solution was performed data analysis and implementation of the application followed by testing on data.

This master’s thesis deals with a modification of existing project which is used as a helpful tool for tracking and measuring digital audio interface I2S. The original design was created by Ing. Martin Stejskal, Polymorphic USB – I2S Interface. Modifications are based on practical one year experience when the device was tested and deals with new requirements for extension. This work describes and justify individual changes of hardware and software part of project.

CU-tree (Coding Unit tree) is an algorithm for adaptive QP (quantization parameter). It runs in the lookahead and decreases the QP of blocks that are heavily referenced by future blocks, taking into account the quality of the prediction and the complexity of the future blocks, approximated by the inter and intra residual. In this study, CU-tree is implemented in c65, an experimental HEVC encoder used internally by Ericsson. The effects of CU-tree are evaluated on the video clips in the HEVC Common test conditions and the performance is compared across c65, x265 and x264. The results are similar across all encoders, with average PSNR (peak signal-to-noise ratio) improvements of 3-10% depending on the fixed QP offsets that are replaced. The runtime is not impaired and improvements to visual quality are expected to be even greater. The algorithm works better at slow speed modes, low bitrates and with source material that is well suited for inter prediction. / CU-tree är en algoritm för adaptiv QP. Den körs under framåtblicken (lookahead) och minskar QP för block som refereras av många framtida block, med hänsyn tagen till prediktionens kvalitet och de framtida blockens komplexitet, approximerat av inter- och intra-skillnaden. I denna studie implementeras CU-tree i c65, en experimentell videokodare som används internt på Ericsson. Effekterna av algoritmen utvärderas på videoklippen i HEVC Common test conditions och prestandan jämförs mellan c65, x265 och x264. Resultaten är liknande i alla videokodare, med genomsnittliga PSNR-förbättringar på 3-10% beroende på vilka fasta QP-offsets som algoritmen ersätter. Körtiden påverkas inte nämnvärt och den subjektiva kvaliteten förbättras troligen ännu mer. Algoritmen fungerar bättre med långsamma hastighetsinställningar, låg bitrate samt videoinnehåll som lämpar sig väl för inter-prediktion.