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Sun, Lei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9

Ng Chong Chon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 100-103). / Abstract in English and Chinese. / 摘要 --- p.iii / Acknowledgments --- p.iv / Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- DMP Architecture --- p.6 / Chapter 2.1 --- Conventional DMP --- p.6 / Chapter 2.1.1 --- Operating Principle --- p.7 / Chapter 2.1.2 --- Disadvantages --- p.10 / Chapter 2.2 --- Pre-processing Clock Architecture --- p.10 / Chapter 2.2.1 --- Operating Principle --- p.11 / Chapter 2.2.2 --- Advantages and Disadvantages --- p.12 / Chapter 2.3 --- Phase-switching Architecture --- p.13 / Chapter 2.3.1 --- Operating Principle --- p.13 / Chapter 2.3.2 --- Advantages and Disadvantages --- p.14 / Chapter 2.4 --- Summary --- p.15 / Chapter Chapter 3 --- Full-Speed Divider Design --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Working Principle --- p.16 / Chapter 3.3 --- Design Issues --- p.18 / Chapter 3.4 --- Device Sizing --- p.19 / Chapter 3.5 --- Layout Considerations --- p.20 / Chapter 3.6 --- Input Sensitivity --- p.22 / Chapter 3.7 --- Modeling --- p.24 / Chapter 3.8 --- Review on Different Divider Designs --- p.28 / Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28 / Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30 / Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32 / Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34 / Chapter 3.9 --- Summary --- p.42 / Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Proposed DMP Topology --- p.46 / Chapter 4.3 --- Circuit Design and Implementation --- p.49 / Chapter 4.4 --- Simulation Results --- p.51 / Chapter 4.5 --- Summary --- p.53 / Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Proposed DMP Topology --- p.56 / Chapter 5.3 --- Circuit Design and Implementation --- p.59 / Chapter 5.3.1 --- Divide-by-4 stage --- p.59 / Chapter 5.3.2 --- TSPC dividers --- p.63 / Chapter 5.3.3 --- Phase-selection Network --- p.63 / Chapter 5.3.4 --- Mode-control Logic --- p.64 / Chapter 5.3.5 --- Duty-cycle Transformer --- p.65 / Chapter 5.3.6 --- Glitch Problem --- p.66 / Chapter 5.3.7 --- Phase-mismatch Problem --- p.70 / Chapter 5.4 --- Simulation Results --- p.70 / Chapter 5.5 --- Summary --- p.74 / Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75 / Chapter 6.1 --- Introduction --- p.75 / Chapter 6.2 --- Proposed DMP Architecture --- p.75 / Chapter 6.3 --- Divide-by-4 Stage --- p.76 / Chapter 6.3.1 --- Current-switch Combining --- p.76 / Chapter 6.3.2 --- Capacitive Load Reduction --- p.77 / Chapter 6.4 --- Simulation Results --- p.81 / Chapter 6.5 --- Summary --- p.83 / Chapter Chapter 7 --- Experimental Results --- p.84 / Chapter 7.1 --- Introduction --- p.84 / Chapter 7.2 --- Equipment Setup --- p.84 / Chapter 7.3 --- Measurement Results --- p.85 / Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85 / Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88 / Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93 / Chapter 7.3 --- Summary --- p.96 / Chapter Chapter 8 --- Conclusions and Future Works --- p.98 / Chapter 8.1 --- Conclusions --- p.98 / Chapter 8.2 --- Future Works --- p.99 / References --- p.100 / Publications --- p.104

In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Previous work at Stanford University has demonstrated that inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise into analog circuits. The low impedance substrate can be treated as a single node over a local area. Switching in the digital circuits produces current transients in the substrate. These transients are subsequently amplified in the analog portions of the overall mixed-mode circuit. Various guard rings and other techniques, including the use of new logic circuit families, have been proposed to suppress this noise. This work demonstrates that by using the capacitance of a forward biased guard ring(s), the substrate noise at a specific frequency(ies) can be reduced by resonating the guard ring capacitance with the substrate lead inductance to provide a very low substrate-to-ground impedance. In this manner, noise at particular frequencies, which are problematic to the analog circuit, can be suppressed. Tuning can be accomplished by varying the current in the forward-biased guard ring diodes. / Graduation date: 1995

The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility. / text

The evolving needs of network carriers are changing the design of optical networks. In order to reduce cost, latency, and power consumption, electrical switches are being replaced with optical switching fabrics at the core of the networks. An example of such a network is an Agile All-Photonic Network (AAPN). / This thesis presents a novel device that was designed to operate as an optical switch within the context of an AAPN network. The device is a Reprogrammable Optical Phase Array (ROPA), and the design consists of applying multiple electric fields of different magnitudes across an electro-optic material in order to create a diffractive optical element. The configuration of the electric fields can change to modify the properties of the diffractive device. / Such a device has a wide range of potential applications, and two different ROPA designs are presented. Both designs are optimized to function as 1xN optical switches. The switches are wavelength tunable and have switching times on the order of microseconds. The ROPA devices consist of two parts: a bulk electro-optic crystal, and a high-voltage CMOS chip for the electrical control of the device. The design, simulation, fabrication and testing of both the electrical and optical components of the devices are presented.

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Thesis (Ph.D)--Physics, Georgia Institute of Technology, 2009. / Committee Co-Chair: Conrad, Edward; Committee Co-Chair: First, Phillip; Committee Member: Carter, Brent; Committee Member: de Heer, Walter; Committee Member: Zangwill, Andrew. Part of the SMARTech Electronic Thesis and Dissertation Collection.