Although the overall levels of harmonics in modern power supply systems are in most of the practical cases still below the prescribed tolerance limits and thresholds (e.g. these stipulated in [IEC 61000-3-2 and 61000-3-12]), the sources of harmonics are constantly increasing in numbers and are expected to increase even more in the future. Some of the examples of modern non-linear power electronic (PE) devices that are expected to be employed on a much wider scale in LV networks in the future include: light-emitting diode (LED) lamps, switched-mode power supplies (SMPS'), electric vehicle battery chargers (EVBCs) and photovoltaic inverters (PVIs), which are all analysed in this thesis. The thesis first reviews the conventional harmonic analysis methods, investigating their applicability to modern PE devices. After that, the two most widely used forms of harmonic models, i.e. component-based models (CBMs) and frequency-domain models (FDMs), are applied for modelling of the four abovementioned types of modern PE devices and their models are fully validated by measurements. The thesis next investigates the impact of supply voltage conditions and operating modes (e.g. low vs high operating powers) on the device characteristics and performance, using both measurements and developed CBMs and FDMs. The obtained results confirm that both supply conditions and operating modes have an impact on the characteristics of most of the considered PE devices, which is taken into account in the developed models and demonstrated on a number of case studies. As the next contribution, the thesis proposes new indices for the evaluation of current waveform distortions, allowing for a separate analysis of contributions of low and high frequency harmonics and interharmonics to the total waveform distortion of PE devices. As the modern PE devices are normally based on high-frequency switching converters or inverters, the impact of circuit topologies and control algorithms on their harmonic emission characteristics and performance is also investigated. Special attention is given to the operation of PE devices at low powers, when there is a significant increase of current waveform distortion, a substantial decrease of efficiency and power factors and when input ac current might lose its periodicity with the supply voltage frequency. This is analysed in detail for SMPS', resulting in the proposal of a new methodology ("operating cycle based method") for evaluating overall performance of PE devices across the entire range of operating powers. Finally, a novel and simple hybrid harmonic modelling technique, allowing for the use of both time-domain and frequency-domain models in the same simulation environment, is proposed and illustrated on the selected case studies. This is accompanied with a frequency-domain aggregation approach, which is applied in the thesis to investigate the impact of increasing numbers of different types of modern PE devices on the LV network. The implementation of the developed hybrid harmonic modelling approach and frequency-domain aggregation technique is demonstrated on the example of a typical (UK) urban generic LV distribution network and used for the analysis of different deployment levels of EVs and PVIs. The presented harmonic modelling framework for individual PE devices and, particularly, for their aggregate models, fills the gap in the existing literature on harmonic modelling and characterisation of modern PE devices, which is important for the correct evaluation of their harmonic interactions and analysis of the impact of their large-scale deployment on the overall network performance.

Dans le domaine des systèmes temps-réel embarqués critiques, les méthodes de conception et de spécification et leurs outils associés doivent permettre le développement de systèmes au comportement temporel déterministe et, par conséquent, reproductible afin de garantir leur sûreté de fonctionnement. Pour atteindre cet objectif, on s’intéresse aux méthodologies de développement basées sur le paradigme Time-Triggered (TT). Dans ce contexte, nombre de propriétés et, en particulier, les contraintes temps-réel de-bout-en-bout, se voient satisfaites par construction. Toutefois, garantir la sûreté de fonctionnement de tels systèmes reste un défi. En général, les outils de développement existants n’assurent pas par construction le respect de l’intégralité des spécifications, celles-ci doivent, en général, être vérifiées à posteriori. Avec la complexité croissante des applications embarquées, celle de leur validation à posteriori devient, au mieux, un facteur majeur dans les coûts de développement et, au pire, tout simplement impossible. Il faut, donc, définir une méthode qui, tout en permettant le développement des systèmes corrects par constructions, structure et simplifie le processus de spécification. Les méthodologies de conception de haut niveau à base de composants, qui permettent la conception et la vérification des systèmes temps-réels critiques, présentent une solution ultime pour la structuration et la simplification du processus de spécification de tels systèmes.L’objectif de cette thèse est d'associer la méthodologie BIP (Behaviour-Interaction-Priority) qui est une approche de conception basée sur composants avec la plateforme d'exécution PharOS, qui est un système d'exploitation temps-réel déterministe orienté sûreté de fonctionnement. Le flot de conception proposé dans cette thèse est une approche transformationnelle qui permet de conserver les propriétés fonctionnelles des modèles originaux de BIP. Il est composé essentiellement de deux étapes. La première étape, paramétrée par un mapping de tâche défini par l'utilisateur, permet de transformer un modèle BIP en un modèle plus restreint qui représente une description haut niveau des implémentations basées sur des primitives de communication TT. La deuxième étape permet la génération du code pour la plateforme PharOS à partir de ce modèle restreint.Un ensemble d'outils a été développé dans cette thèse afin d'automatiser la plupart des étapes du flot de conception proposé. Ceci a permis de tester cette approche sur deux cas d'étude industriels ; un simulateur de vol et un relais de protection moyenne tension. Dans les deux applications, on vise à comparer les fonctionnalités du modèle BIP avec celles du modèle intermédiaire et du code généré. On fait varier les stratégies de mapping de tâche dans la première application, afin de tester leur impact sur le code généré. Dans la deuxième application, on étudie l'impact de la transformation sur le code généré en comparant quelques aspects de performance du code générer avec ceux d'une version de l'application qui a été développée manuellement. / In hard real-time embedded systems, design and specification methods and their associated tools must allow development of temporally deterministic systems to ensure their safety. To achieve this goal, we are specifically interested in methodologies based on the Time-Triggered (TT) paradigm. This paradigm allows preserving by construction number of properties, in particular, end-to-end real-time constraints. However, ensuring correctness and safety of such systems remains a challenging task. Existing development tools do not guarantee by construction specification respect. Thus, a-posteriori verification of the application is generally a must. With the increasing complexity of embedded applications, their a-posteriori validation becomes, at best, a major factor in the development costs and, at worst, simply impossible. It is necessary, therefore, to define a method that allows the development of correct-by-construction systems while simplifying the specification process.High-level component-based design frameworks that allow design and verification of hard real-time systems are very good candidates for structuring the specification process as well as verifying the high-level model.The goal of this thesis is to couple a high-level component-based design approach based on the BIP (Behaviour-Interaction-Priority) framework with a safety-oriented real-time execution platform implementing the TT approach (the PharOS Real-Time Operating System). To this end, we propose an automatic transformation process from BIPmodels into applications for the target platform (i.e. PharOS).The process consists in a two-step semantics-preserving transformation. The first step transforms a BIP model coupled to a user-defined task mapping into a restricted one, which lends itself well to an implementation based on TT communication primitives. The second step transforms the resulting model into the TT implementation provided by the PharOS RTOS.We provide a tool-flow that automates most of the steps of the proposed approach and illustrate its use on an industrial case study for a flight Simulator application and a medium voltage protection relay application. In both applications, we compare functionalities of both original, intermediate and final model in order to confirm the correctness of the transformation. For the first application, we study the impact of the task mapping on the generated implementation. And for the second application, we study the impact of the transformation on some performance aspects compared to a manually written version.

<p dir="ltr">Composite Plate Shear Wall/ Concrete Filled (C-PSW/CF), also referred to as SpeedCore walls, are being used as innovative shear wall commercial high-rise buildings. These walls offer advantages such as modularity and construction schedule contraction. The cross-section of C- PSWs/CF consists of concrete infill sandwiched between the steel faceplates, where the steel plates are tied together by steel tie bars. Elevated temperatures will result in a deterioration in the mechanical properties of steel and concrete during a fire event in buildings. Such degradation can lead to stability-related failure of structural components. Composite floors are connected to these walls through simple shear connections. The floor-to-wall connections will be exposed to elevated temperatures, which may result in connection failure and progressive collapse of structures.</p><p dir="ltr">Designing SpeedCore walls without fire protection raises concerns regarding the performance of other structural components connected to SpeedCore walls under fire loading including composite floor systems and wall-to-floor connections. Numerical studies conducted on the connections and the floor systems indicated that these structural components undergo thermal compression forces during heating and tensile forces during the cooling phases of a fire event. The goal of this research was to develop an approach for performance-based fire resistance design of complete floor systems consisting of SpeedCore walls, composite floor slabs, and wall-to-floor connections.</p><p dir="ltr">This research includes experimental and numerical analyses to gain insight into the behavior of the floor-to-SpeedCore wall connections under fire and gravity loading. The specimens included steel beams connected to SpeedCore walls through simple shear connections. Three types of floor-to-wall connections were tested including connections with through-plate, reinforcing plate, and unreinforced plate. The parameters considered in the test matrix included: connection type, temperature, loading angle, and loading direction. These parameters in the test matrix were based on results obtained from previous numerical and experimental studies in the literature. The experimental results can fill the existing knowledge gap on floor-to-wall connections for steel-concrete composite members, develop design recommendations, and benchmark numerical models.</p><p dir="ltr">Numerical models were developed to simulate the behavior of the connections (member level) and whole structures (structure level) at ambient and elevated temperatures. Finite Element (FE) analysis and Component-based Models (CB) were utilized to develop the numerical models. The developed models were benchmarked by comparing the obtained numerical results with experimental data reported in the literature. FE models have been validated at two different levels, namely member level, and system level. The performance of the designed connection for the archetype structures was studied using benchmarked FE and CB models. The behavior of various wall-to-floor connections with different steel plate (C-PSW/CF) detailing was investigated.</p><p dir="ltr">Benchmarked numerical models were used to perform a parametric study to evaluate the performance of these connections. UP connection detail was used to perform the study due to its promising experimental performance, which does not need any special detail or plate reinforcement. The study was performed by evaluating the effects of critical parameters on the connection behavior namely, bolt size, target temperature, loading angles, and loading direction</p>