Today's supercomputers and cloud systems run many data-centric applications such as machine learning, graph algorithms, and cognitive processing, which have large data footprints and complex data access patterns. With computational capacity of large-scale systems projected to rise up to 50GFLOPS/W, the target energy-per-bit budget for data movement is expected to reach as low as 0.1pJ/bit, assuming 200bits/FLOP for data transfers. This tight energy budget impacts the design of both chip-scale networks and main memory systems. Conventional electrical links used in chip-scale networks (0.5-3pJ/bit) and DRAM systems used in main memory (>30pJ/bit) fail to provide sustained performance at low energy budgets. This thesis builds on the promising research on silicon-photonic technology to design system architectures and system management policies for chip-scale networks and main memory systems. The adoption of silicon-photonic links as chip-scale networks, however, is hampered by the high sensitivity of optical devices towards thermal and process variations. These device sensitivities result in high power overheads at high-speed communications. Moreover, applications differ in their resource utilization, resulting in application-specific thermal profiles and bandwidth needs. Similarly, optically-controlled memory systems designed using conventional electrical-based architectures require additional circuitry for electrical-to-optical and optical-to-electrical conversions within memory. These conversions increase the energy and latency per memory access. Due to these issues, chip-scale networks and memory systems designed using silicon-photonics technology leave much of their benefits underutilized. This thesis argues for the need to rearchitect memory systems and redesign network management policies such that they are aware of the application variability and the underlying device characteristics of silicon-photonic technology. We claim that such a cross-layer design enables a high-throughput and energy-efficient unified silicon-photonic link and main memory system. This thesis undertakes the cross-layer design with silicon-photonic technology in two fronts. First, we study the varying network bandwidth requirements across different applications and also within a given application. To address this variability, we develop bandwidth allocation policies that account for application needs and device sensitivities to ensure power-efficient operation of silicon-photonic links. Second, we design a novel architecture of an optically-controlled main memory system that is directly interfaced with silicon-photonic links using a novel read and write access protocol. Such a system ensures low-energy and high-throughput access from the processor to a high-density memory. To further address the diversity in application memory characteristics, we explore heterogeneous memory systems with multiple memory modules that provide varied power-performance benefits. We design a memory management policy for such systems that allocates pages at the granularity of memory objects within an application.

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Performance unpredictability of the cloud hinders widespread adoption of cloud systems and adversely impacts costs and revenue. To mitigate this challenge, cloud systems typically incorporate monitoring and tracing mechanisms to collect a diverse set of metrics on applications' state to facilitate the analysis of performance fluctuations. Drawing on this collected data, engineers devote considerable effort to diagnosing performance issues and expediting the delivery of superior-quality software to enhance performance, aligning with changing demands. To capture unanticipated performance problems, engineers utilize state-of-the-art diagnostic systems to meticulously trace and record behavior of distributed applications running on cloud. However, this level of detailed tracing incurs considerable costs in terms of storage, computation, and network overheads. Even after engineers have resolved these performance problems, they may face challenges in deploying new code to the cloud. Gradual deployment approaches are available to mitigate risk by enabling faulty versions to be rolled back, but these systems lack the necessary statistical sophistication to accurately assess and compare application versions, potentially leading to further performance issues. This thesis argues that integrating automated, statistically-driven methods is imperative to achieve substantial improvements in efficiency when diagnosing application performance and delivering new code in the cloud. This vision has the potential to enable efficient and proactive performance management beyond the state-of-the-art by reducing time, effort, and cost spent on diagnosis and code delivery. To support this vision, the thesis makes two specific contributions. First, we demonstrate that dynamically adjusting instrumentation using statistically-driven techniques significantly enhances diagnosis efficiency. Our distributed tracing approach enables accurate tracing of sources of performance issues using only a small fraction of the available tracing instrumentation. Second, we demonstrate an online learning-based approach that intelligently adjusts the user traffic split among competing deployments, substantially improves code delivery efficiency. Our online experimentation approach reduces performance variations by directing user traffic to the optimal deployment during code delivery. / 2025-05-24T00:00:00Z

One of the great advances in computation over the last 20 years is the availability, connectivity, and growth of datacenters. These advances in the datacenter have motivated research, development, and adoption of new techniques to improve the overall performance of datacenter activities. Such techniques include virtualization, software defined networking (SDN), distributed computing, platform-as-a-service (PaaS), serverless computing, and many more. Continued improvements and support for all these datacenter applications has required a re-imagining of the current connected environment into one that is more data focused, where computation is everywhere, and high performance networks connect all resources together. A key part of this evolution is making network fabrics more intelligent by substituting traditional network interface cards (NICs) with SmartNICs; these create opportunities to move computation away from compute nodes and into the network. Field programmable gate arrays (FPGAs) play a significant role in realizing these new opportunities in the network fabric as they have both compute and communication hardware. In this thesis, we investigate performance and usability of network FPGAs and demonstrate their utility with case studies in security and privacy for tenants in the datacenter. We propose an approach to achieve a new level of security and performance through the use of reconfigurable hardware available with network attached FPGA SmartNICs. We first show how FPGAs directly connected to high-bandwidth network resources can reduce the network load through function offload onto FPGAs. We then demonstrate the capabilities of FPGA SmartNICs to perform in-line packet acceleration functions as well as application acceleration without host processing. Next, we improve the security of the datacenter through network isolation techniques and secure data processing between tenants co-located in the same datacenter. To this end, we accelerate a state-of-the-art cryptographic algorithm, Secret Sharing Multi-Party Computation (MPC), using FPGAs. Our FPGA accelerated Secret Sharing MPC uses at least a 10x less computing resources compared to the original design using CPUs. To demonstrate the real-world advantages of leveraging network-attached FPGA SmartNICs, we present three unique applications of these FPGAs specifically for security. First, we improve the performance of datacenter nodes on CPUs by offloading common packet functions such as remote memory access and packet fragmentation. Second, towards the goal of providing private cloud enclaves, we propose a method of securing tenant private networks with FPGA SmartNICs. Finally, we leverage FPGA SmartNICs to efficiently perform joint confidential data processing between cooperating organizations.

The research involved optimizing the space and bounding the output time by the output size in categorical range reporting of points within the given rectangle query Q in two dimension using wavelet trees and range counting. The time taken to report those points and space to tore n points in set S can be done using wavelet tree and range counting. Consider set S consisting of n points in two-dimension. An orthogonal range reporting query rectangle Q = [a,b] x [c,d] on set S is sent to report the set of points in S which interacts with the query rectangle[Q]. The time taken to report these points is dependent on the output size. The categorical range reporting is an extension of orthogonal range reporting, where each point (xi; yi) in S is associated with a category c[i] belongs to [sigma] and the query is to report the set of distinct categories within the query region [a,b] x [c,d] once. In this paper, we present a new solution for this problem using wavelet trees. The points in S associated with categories are stored in a wavelet tree structure. Wavelet tree structure consists of bit map for these categories. To report the categories in the given rectangle query Q, rank and select operations on the wavelet tree is applied. It was observed that the space taken by the structure was O(n log sigma) space and query time is O(k log n log sigma). Notice that the new result is more efficient in space when log sigma = O(log n). The study provides a new and efficient way of storing large dataset and also bounds the time complexity by the output size k.