No description available.

This thesis presents an analysis on DC-to-DC converters using the switch-mode technology which produces very high switching speed and very high power handling capabilities. It introduces a steady state analysis of the buck, boost, and buck-boost converters operating in both continuous conduction mode and discontinuous conduction mode, as well as a discussion of some other isolated switch-mode converters, mainly the flyback, forward, push-pull, half and full-bridge converters. Furthermore, the thesis investigates the effect of the non-idealities of some of the components, such as the inductor series resistor, Equivalent Series Resistor (ESR) of the output capacitor, diode drop voltage, transistor switching and conducting losses. Spread-sheet utilization will be used to show the effect of these components on the voltage gain of these converters.

This project explores the various aspects of real-time data analysis, and how it can be applied to a simple interface through which a user can access traffic information. This thesis involves the development of discrete-event simulation models of the traffic patterns on Interstate 4 (I-4) in Orlando. The information gathered from these patterns was used to create a simulated I-4 Web Map (containing virtual sensors). The simulation was exercised to develop and build an aggregator which reads, interprets and deciphers the information and feedback obtained from the I-4 Web Map. This information is then expressed in English words. These words, in turn, are communicated to the user by voice via a telephone. A prototype was built selecting a subsection of the simulated I-4 Web Map in Orlando. This is summarized in this thesis along with different guidelines necessary for expanding the system, the strength of the current leading-edge technologies, and a foundation to start exploring more sophisticated models.

One of the great advances in computation over the last 20 years is the availability, connectivity, and growth of datacenters. These advances in the datacenter have motivated research, development, and adoption of new techniques to improve the overall performance of datacenter activities. Such techniques include virtualization, software defined networking (SDN), distributed computing, platform-as-a-service (PaaS), serverless computing, and many more. Continued improvements and support for all these datacenter applications has required a re-imagining of the current connected environment into one that is more data focused, where computation is everywhere, and high performance networks connect all resources together. A key part of this evolution is making network fabrics more intelligent by substituting traditional network interface cards (NICs) with SmartNICs; these create opportunities to move computation away from compute nodes and into the network. Field programmable gate arrays (FPGAs) play a significant role in realizing these new opportunities in the network fabric as they have both compute and communication hardware. In this thesis, we investigate performance and usability of network FPGAs and demonstrate their utility with case studies in security and privacy for tenants in the datacenter. We propose an approach to achieve a new level of security and performance through the use of reconfigurable hardware available with network attached FPGA SmartNICs. We first show how FPGAs directly connected to high-bandwidth network resources can reduce the network load through function offload onto FPGAs. We then demonstrate the capabilities of FPGA SmartNICs to perform in-line packet acceleration functions as well as application acceleration without host processing. Next, we improve the security of the datacenter through network isolation techniques and secure data processing between tenants co-located in the same datacenter. To this end, we accelerate a state-of-the-art cryptographic algorithm, Secret Sharing Multi-Party Computation (MPC), using FPGAs. Our FPGA accelerated Secret Sharing MPC uses at least a 10x less computing resources compared to the original design using CPUs. To demonstrate the real-world advantages of leveraging network-attached FPGA SmartNICs, we present three unique applications of these FPGAs specifically for security. First, we improve the performance of datacenter nodes on CPUs by offloading common packet functions such as remote memory access and packet fragmentation. Second, towards the goal of providing private cloud enclaves, we propose a method of securing tenant private networks with FPGA SmartNICs. Finally, we leverage FPGA SmartNICs to efficiently perform joint confidential data processing between cooperating organizations.

The research involved optimizing the space and bounding the output time by the output size in categorical range reporting of points within the given rectangle query Q in two dimension using wavelet trees and range counting. The time taken to report those points and space to tore n points in set S can be done using wavelet tree and range counting. Consider set S consisting of n points in two-dimension. An orthogonal range reporting query rectangle Q = [a,b] x [c,d] on set S is sent to report the set of points in S which interacts with the query rectangle[Q]. The time taken to report these points is dependent on the output size. The categorical range reporting is an extension of orthogonal range reporting, where each point (xi; yi) in S is associated with a category c[i] belongs to [sigma] and the query is to report the set of distinct categories within the query region [a,b] x [c,d] once. In this paper, we present a new solution for this problem using wavelet trees. The points in S associated with categories are stored in a wavelet tree structure. Wavelet tree structure consists of bit map for these categories. To report the categories in the given rectangle query Q, rank and select operations on the wavelet tree is applied. It was observed that the space taken by the structure was O(n log sigma) space and query time is O(k log n log sigma). Notice that the new result is more efficient in space when log sigma = O(log n). The study provides a new and efficient way of storing large dataset and also bounds the time complexity by the output size k.

Unlike typical computing systems, applications in real-time systems require strict timing guarantees. In the pursuit of providing guarantees, the complex dynamic behaviors of these systems are simplified using models to keep the analysis tractable. In order to guarantee safety, such models often involve pessimistic assumptions. While the amount of pessimism was reasonable for simple computing platforms, for modern platforms the pessimism involves ignoring features that improve performance such as cache usage, instruction pipelines, and more. In this work, we explore routing and scheduling problems in real-time systems, where the uncertainties in the operation are carefully accounted for by complex models and/or the routing and scheduling algorithms proposed. For real-time scheduling problems, we incorporate the execution time distribution into the task model to design a system that can meet the maximum permitted incidences of failure per hour. We also consider the case where no failure is permitted and all jobs in the system must be scheduled without violating their timing requirements, throughout their operation. It is achieved on a varying speed multiprocessor platform. For real-time routing problems, we consider graphs whose edge cost distribution is dynamic and the routed packets have deadlines to be met. We then extend this problem to the case where the initial (discrete) distribution of the edge costs is fully known. We propose a technique to safely incorporate a reinforcement learning strategy once the system deviates from its initial distribution. Finally, we focus on practical improvements to the popular and optimal earliest deadline first scheduling algorithm, upon a uniprocessor setting. Specifically, we develop techniques to quantify and utilize the idle times to handle uncertainties in the form of additional run-time workloads, arbitrary self-suspensions, and execution time estimate overruns.

While Internet of Things (IoT) sensors offer numerous benefits in diverse applications, they are limited by stringent constraints in energy, processing area and memory. These constraints are especially challenging within applications such as Compressive Sensing (CS) and Machine Learning (ML) via Deep Neural Networks (DNNs), which require dot product computations on large data sets. A solution to these challenges has been offered by the development of crossbar array architectures, enabled by recent advances in spintronic devices such as Magnetic Tunnel Junctions (MTJs). Crossbar arrays offer a compact, low-energy and in-memory approach to dot product computation in the analog domain by leveraging intrinsic signal-transfer characteristics of the embedded MTJ devices. The first phase of this dissertation research seeks to build on these benefits by optimizing resource allocation within spintronic crossbar arrays. A hardware approach to non-uniform CS is developed, which dynamically configures sampling rates by deriving necessary control signals using circuit parasitics. Next, an alternate approach to non-uniform CS based on adaptive quantization is developed, which reduces circuit area in addition to energy consumption. Adaptive quantization is then applied to DNNs by developing an architecture allowing for layer-wise quantization based on relative robustness levels. The second phase of this research focuses on extension of the analog computation paradigm by development of an operational amplifier-based arithmetic unit for generalized scalar operations. This approach allows for 95% area reduction in scalar multiplications, compared to the state-of-the-art digital alternative. Moreover, analog computation of enhanced activation functions allows for significant improvement in DNN accuracy, which can be harnessed through triple modular redundancy to yield 81.2% reduction in power at the cost of only 4% accuracy loss, compared to a larger network. Together these results substantiate promising approaches to several challenges facing the design of future IoT sensors within the targeted applications of CS and ML.

No description available.

No description available.

Machine learning (ML) is now omnipresent in all spheres of life. The use of deep neural networks (DNNs) for ML has gained popularity over the past few years. This is because DNNs are capable of efficiently solving complex problems such as image processing, object detection, language processing, etc. To train these DNN workloads, graphics process- ing units (GPUs) have become the most widely used platform. A GPU can support a large number of parallel threads that execute simultaneously to achieve a very high throughput. However, as the sizes of the DNN workloads grow, a single GPU is no longer adequate to provide fast training, and developers resort to using multi-GPU (MGPU) systems that can reduce the training time significantly. Consequently, to keep pace with the growth of DNN applications, GPU vendors are actively developing novel and efficient MGPU systems. To better understand the challenges associated with designing MGPU systems for DNN workloads, in this thesis, we first present our efforts to understand the behavior of the DNN workloads, in particular, the training of DNN workloads on MGPU systems. Using the DNN workloads as benchmarks, we observe the evolution of MGPU system architecture. Based on our profiling and characterization of DNN workloads on existing high-performance MGPU systems, we identify the computation- and communication- intensiveness of the DNN workloads and the hardware- and software-level inefficiencies present in the existing MGPU systems. We find that the data movement across multiple GPUs and high remote data access cost leading to NUMA effects, data duplication, and inefficient use of GPU memory leading to memory capacity issues, and the complexity in programming MGPUs pose serious limitations in the execution of ever-scaling DNN workloads on MGPU systems. To overcome the limitations of existing MGPU systems, we propose to unify the main memory of GPUs to design an MGPU system with true shared memory (MGPU-TSM). Our proposed MGPU-TSM system demonstrates a significant performance boost (3.8× for a 4 GPU system) over the best-performing existing MGPU system. This is because MGPU-TSM system eliminates the NUMA effects and the necessity for data duplication. To provide seamless data sharing across multiple GPUs and ease programming of MGPU- TSM, we propose a light-weight coherence protocol called MGCC. MGCC is a timestamp- based protocol that provides both intra- and inter-GPU coherence. We implement a number of hardware features including unified memory controller, request tracker and timestamp storage unit to support MGCC. Using both standard and synthetic stress benchmarks, we evaluate the MGPU-TSM system with MGCC leveraging sequential as well as relaxed consistency. Our evaluation of a 4-GPU system using MGPUSim simulator suggests that our proposed coherent MGPU system achieves up to 3.8× improved performance than current best-performing MGPU system while the stress tests performed using synthetic benchmarks suggests that MGCC leads to up to 46.1% performance overhead.