In this thesis, a novel load-balancing technique for local or metro-area traffic is proposed in mesh-style topologies. The technique uses Software Defined Networking (SDN) architecture with virtual local area network (VLAN) setups typically seen in a campus or small-to-medium enterprise environment. This was done to provide a possible solution or at least a platform to expand on for the load-balancing dilemma that network administrators face today. The transport layer protocol Multi-Path TCP (MPTCP) coupled with IP aliasing is also used. The trait of MPTCP of forming multiple subflows from sender to receiver depending on the availability of IP addresses at either the sender or receiver helps to divert traffic in the subflows across all available paths. The combination of MPTCP subflows with IP aliasing enables spreading out of the traffic load across greater number of links in the network, and thereby achieving load balancing and better network utilization. The traffic formed of each subflow would be forwarded across the network based on Hamiltonian 'paths' which are created in association with each switch in the topology which are directly connected to hosts. The amount of 'paths' in the topology would also depend on the number of VLANs setup for the hosts in the topology. This segregation would allow for network administrators to monitor network utilization across VLANs and give the ability to balance load across VLANs. We have devised several experiments in Mininet, and the experimentation showed promising results with significantly better throughput and network utilization compared to cases where normal TCP was used to send traffic from source to destination. Our study clearly shows the advantages of using MPTCP for load balancing purposes in SDN type architectures and provides a platform for future research on using VLANs, SDN, and MPTCP for network traffic management.

This thesis presents a robust, flexible and real-time architecture for Software-in-the-Loop (SIL) testing of connected vehicle safety applications. Emerging connected and automated vehicles (CAV) use sensing, communication and computing technologies in the design of a host of new safety applications. Testing and verification of these applications is a major concern for the automotive industry. The CAV safety applications work by sharing their state and movement information over wireless communication links. Vehicular communication has fueled the development of various Cooperative Vehicle Safety (CVS) applications. Development of safety applications for CAV requires testing in many different scenarios. However, the recreation of test scenarios for evaluating safety applications is a very challenging task. This is mainly due to the randomness in communication, difficulty in recreating vehicle movements precisely, and safety concerns for certain scenarios. We propose to develop a standalone Remote Vehicle Emulator (RVE) that can reproduce V2V messages of remote vehicles from simulations or from previous tests, while also emulating the over the air behavior of multiple communicating nodes. This is expected to significantly accelerate the development cycle. RVE is a unique and easily configurable emulation cum simulation setup to allow Software in the Loop (SIL) testing of connected vehicle applications in a realistic and safe manner. It will help in tailoring numerous test scenarios, expediting algorithm development and validation as well as increase the probability of finding failure modes. This, in turn, will help improve the quality of safety applications while saving testing time and reducing cost. The RVE architecture consists of two modules, the Mobility Generator, and the Communication emulator. Both of these modules consist of a sequence of events that are handled based on the type of testing to be carried out. The communication emulator simulates the behavior of MAC layer while also considering the channel model to increase the probability of successful transmission. It then produces over the air messages that resemble the output of multiple nodes transmitting, including corrupted messages due to collisions. The algorithm that goes inside the emulator has been optimized so as to minimize the communication latency and make this a realistic and real-time safety testing tool. Finally, we provide a multi-metric experimental evaluation wherein we verified the simulation results with an identically configured ns3 simulator. With the aim to improve the quality of testing of CVS applications, this unique architecture would serve as a fundamental design for the future of CVS application testing.

To facilitate big data processing, many distributed analytic frameworks and storage systems such as Apache Hadoop, Apache Hama, Apache Spark and Hadoop Distributed File System (HDFS) have been developed. Currently, many researchers are conducting research to either make them more scalable or enabling them to support more analysis applications. In my PhD study, I conducted three main works in this topic, which are minimizing the communication delay in Apache Hama, minimizing the memory space and computational overhead in HDFS and minimizing the disk I/O overhead for approximation applications in Hadoop ecosystem. Specifically, In Apache Hama, communication delay makes up a large percentage of the overall graph processing time. While most recent research has focused on reducing the number of network messages, we add a runtime communication and computation scheduler to overlap them as much as possible. As a result, communication delay can be mitigated. In HDFS, the block location table and its corresponding maintenance could occupy more than half of the memory space and 30% of processing capacity in master node, which severely limit the scalability and performance of master node. We propose Deister that uses deterministic mathematical calculations to eliminate the huge table for storing the block locations and its corresponding maintenance. My third work proposes to enable both efficient and accurate approximations on arbitrary sub-datasets of a large dataset. Existing offline sampling based approximation systems are not adaptive to dynamic query workloads and online sampling based approximation systems suffer from low I/O efficiency and poor estimation accuracy. Therefore, we develop a distribution aware method called Sapprox. Our idea is to collect the occurrences of a sub-dataset at each logical partition of a dataset (storage distribution) in the distributed system at a very small cost, and make good use of such information to facilitate online sampling.

In this work, we explore the various Brain Neuron tracking techniques, one of the most significant applications of Diffusion Tensor Imaging. Tractography is a non-invasive method to analyze underlying tissue micro-structure. Understanding the structure and organization of the tissues facilitates a diagnosis method to identify any aberrations which can occur within tissues due to loss of cell functionalities, provides acute information on the occurrences of brain ischemia or stroke, the mutation of certain neurological diseases such as Alzheimer, multiple sclerosis and so on. Under all these circumstances, accurate localization of the aberrations in efficient manner can help save a life. Following up with the limitations introduced by the current Tractography techniques such as computational complexity, reconstruction errors during tensor estimation and standardization, we aim to elucidate these limitations through our research findings. We introduce an End to End Deep Learning framework which can accurately estimate the most probable likelihood orientation at each voxel along a neuronal pathway. We use Probabilistic Tractography as our baseline model to obtain the training data and which also serve as a Tractography Gold Standard for our evaluations. Through experiments we show that our Deep Network can do a significant improvement over current Tractography implementations by reducing the run-time complexity to a significant new level. Our architecture also allows for variable sized input DWI signals eliminating the need to worry about memory issues as seen with the traditional techniques. The advantage of this architecture is that it is perfectly desirable to be processed on a cloud setup and utilize the existing multi GPU frameworks to perform whole brain Tractography in minutes rather than hours. The proposed method is a good alternative to the current state of the art orientation estimation technique which we demonstrate across multiple benchmarks.

Hashing for similarity search is one of the most widely used methods to solve the approximate nearest neighbor search problem. In this method, one first maps data items from a real valued high-dimensional space to a suitable low dimensional binary code space and then performs the approximate nearest neighbor search in this code space instead. This is beneficial because the search in the code space can be solved more efficiently in terms of runtime complexity and storage consumption. Obviously, for this method to succeed, it is necessary that similar data items be mapped to binary code words that have small Hamming distance. For real-world data such as images, one usually proceeds as follows. For each data item, a pre-processing algorithm removes noise and insignificant information and extracts important discriminating information to generate a feature vector that captures the important semantic content. Next, a vector hash function maps this real valued feature vector to a binary code word. It is also possible to use the raw feature vectors afterwards to further process the search result candidates produced by binary hash codes. In this dissertation we focus on the following. First, developing a learning based counterpart for the MinHash hashing algorithm. Second, presenting a new unsupervised hashing method UmapHash to map the neighborhood relations of data items from the feature vector space to the binary hash code space. Finally, an application of the aforementioned hashing methods for rapid face image recognition.

High-Level Synthesis (HLS) tools are a set of algorithms that allow programmers to obtain implementable Hardware Description Language (HDL) code from specifications written high-level, sequential languages such as C, C++, or Java. HLS has allowed programmers to code in their preferred language while still obtaining all the benefits hardware acceleration has to offer without them needing to be intimately familiar with the hardware platform of the accelerator. In this work we summarize and expand upon several of our approaches to improve the automatic memory banking capabilities of HLS tools targeting reconfigurable architectures, namely Field-Programmable Gate Arrays or FPGA's. We explored several approaches to automatically find the optimal partition factor and a usable banking scheme for stencil kernels including a tessellation based approach using multiple families of hyperplanes to do the partitioning which was able to find a better banking factor than current state-of-the-art methods and a graph theory methodology that allowed us to mathematically prove the optimality of our banking solutions. For non-stencil kernels we relaxed some of the conditions in our graph-based model to propose a best-effort solution to arbitrarily reduce memory access conflicts (simultaneous accesses to the same memory bank). We also proposed a non-linear transformation using prime factorization to convert a small subset of non-stencil kernels into stencil memory accesses, allowing us to use all previous work in memory partition to them. Our approaches were able to obtain better results than commercial tools and state-of-the-art algorithms in terms of reduced resource utilization and increased frequency of operation. We were also able to obtain better partition factors for some stencil kernels and usable baking schemes for non-stencil kernels with better performance than any applicable existing algorithm.

Systems with nonlinear dynamics are theoretically constrained to the realm of nonlinear analysis and design, while explicit constraints are expressed as equalities or inequalities of state, input, and output vectors of differential equations. Few control designs exist for systems with such explicit constraints, and no generalized solution has been provided. This dissertation presents general techniques to design stabilizing controls for a specific class of nonlinear systems with constraints on input and output, and verifies that such designs are straightforward to implement in selected applications. Additionally, a closed-form technique for an open-loop problem with unsolvable dynamic equations is developed. Typical optimal control methods cannot be readily applied to nonlinear systems without heavy modification. However, by embedding a novel control framework based on barrier functions and feedback linearization, well-established optimal control techniques become applicable when constraints are imposed by the design in real-time. Applications in power systems and aircraft control often have safety, performance, and hardware restrictions that are combinations of input and output constraints, while cryogenic memory applications have design restrictions and unknown analytic solutions. Most applications fall into a broad class of systems known as passivity-short, in which certain properties are utilized to form a structural framework for system interconnection with existing general stabilizing control techniques. Previous theoretical contributions are extended to include constraints, which can be readily applied to the development of scalable system networks in practical systems, even in the presence of unknown dynamics. In cases such as these, model identification techniques are used to obtain estimated system models which are guaranteed to be at least passivity-short. With numerous analytic tools accessible, a data-driven nonlinear control design framework is developed using model identification resulting in passivity-short systems which handles input and output saturations. Simulations are presented that prove to effectively control and stabilize example practical systems.

We propose a self-adaptive genetic algorithm, called SAGA, for the purposes of improving the usability of genetic algorithms on both static and dynamic problems. Self-adaption can improve usability by automating some of the parameter tuning for the algorithm, a difficult and time-consuming process on canonical genetic algorithms. Reducing or simplifying the need for parameter tuning will help towards making genetic algorithms a more attractive tool for those who are not experts in the field of evolutionary algorithms, allowing more people to take advantage of the problem solving capabilities of a genetic algorithm on real-world problems. We test SAGA and analyze its the behavior on a variety of problems. First we test on static test problems, where our focus is on usability improvements as measured by the number of parameter configurations to tune and the number of fitness evaluations conducted. On the static problems, SAGA is compared to a canonical genetic algorithm. Next, we test on dynamic test problems, where the fitness landscape varies over the course of the problem's execution. The dynamic problems allows us to examine whether self-adaptation can effectively react to ever-changing and unpredictable problems. On the dynamic problems, we compare to a canonical genetic algorithm as well as other genetic algorithm methods that are designed or utilized specifically for dynamic problems. Finally, we test on a real-world problem pertaining to Medicare Fee-For-Service payments in order to validate the real-world usefulness of SAGA. For this real-world problem, we compare SAGA to both a canonical genetic algorithm and logistic regression, the standard method for this problem in the field of healthcare informatics. We find that this self-adaptive genetic algorithm is successful at improving usability through a large reduction of parameter tuning while maintaining equal or superior results on a majority of the problems tested. The large reduction of parameter tuning translates to large time savings for users of SAGA. Furthermore, self-adaptation proves to be a very capable mechanisms for dealing with the difficulties of dynamic environment problems as observed by the changes to parameters in response to changes in the fitness landscape of the problem.

New approaches are sought to maximize the signal sensing and reconstruction performance of Internet-of-Things (IoT) devices while reducing their dynamic and leakage energy consumption. Recently, Compressive Sensing (CS) has been proposed as a technique aimed at reducing the number of samples taken per frame to decrease energy, storage, and data transmission overheads. CS can be used to sample spectrally-sparse wide-band signals close to the information rate rather than the Nyquist rate, which can alleviate the high cost of hardware performing sampling in low-duty IoT applications. In my dissertation, I am focusing mainly on the adaptive signal acquisition and conversion circuits utilizing spin-based devices to achieve a highly-favorable range of accuracy, bandwidth, miniaturization, and energy trade-offs while co-designing the CS algorithms. The use of such approaches specifically targets new classes of Analog to Digital Converter (ADC) designs providing Sampling Rate (SR) and Quantization Resolution (QR) adapted during the acquisition by a cross-layer strategy considering both signal and hardware-specific constraints. Extending CS and Non-uniform CS (NCS) methods using emerging devices is highly desirable. Among promising devices, the 2014 ITRS Magnetism Roadmap identifies nanomagnetic devices as capable post-CMOS candidates, of which Magnetic Tunnel Junctions (MTJs) are reaching broader commercialization. Thus, my doctoral research topic is well-motivated by the established aims of academia and industry. Furthermore, the benefits of alternatives to von-Neumann architectures are sought for emerging applications such as IoT and hardware-aware intelligent edge devices, as well as the application of spintronics for neuromorphic processing. Thus, in my doctoral research, I have also focused on realizing post-fabrication adaptation, which is ubiquitous in post-Moore approaches, as well as mission-critical, IoT, and neuromorphic applications.

Compressive Sensing (CS) is a signal processing technique which reduces the number of samples taken per frame to decrease energy, storage, and data transmission overheads, as well as reducing time taken for data acquisition in time-critical applications. The tradeoff in such an approach is increased complexity of signal reconstruction. While several algorithms have been developed for CS signal reconstruction, hardware implementation of these algorithms is still an area of active research. Prior work has sought to utilize parallelism available in reconstruction algorithms to minimize hardware overheads; however, such approaches are limited by the underlying limitations in CMOS technology. Herein, the MFPA (Mixed-signal Field Programmable Array) approach is presented as a hybrid spin-CMOS reconfigurable fabric specifically designed for implementation of CS data sampling and signal reconstruction. The resulting fabric consists of 1) slice-organized analog blocks providing amplifiers, transistors, capacitors, and Magnetic Tunnel Junctions (MTJs) which are configurable to achieving square/square root operations required for calculating vector norms, 2) digital functional blocks which feature 6-input clockless lookup tables for computation of matrix inverse, and 3) an MRAM-based nonvolatile crossbar array for carrying out low-energy matrix-vector multiplication operations. The various functional blocks are connected via a global interconnect and spin-based analog-to-digital converters. Simulation results demonstrate significant energy and area benefits compared to equivalent CMOS digital implementations for each of the functional blocks used: this includes an 80% reduction in energy and 97% reduction in transistor count for the nonvolatile crossbar array, 80% standby power reduction and 25% reduced area footprint for the clockless lookup tables, and roughly 97% reduction in transistor count for a multiplier built using components from the analog blocks. Moreover, the proposed fabric yields 77% energy reduction compared to CMOS when used to implement CS reconstruction, in addition to latency improvements.