Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph.D.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 123-128)

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Flexible and adaptive quality of service (QoS) is desirable for real-time multimedia applications. Suppose a multimedia system is supporting a 30 frame/second video stream which is using a network bandwidth of 2 Mbps, and due to network congestion the network bandwidth is reduced to 1 Mbps. It is desirable that the system supports graceful adaptation of quality of the video stream, for example, by reducing the frame rate to 15 frame/second. The focus of this dissertation is to investigate the design of an adaptive multimedia system (AMS) with multiple concurrent sessions, where the quality of individual sessions is dynamically adapted to the available resources and to the run-time user preferences. We propose the Utility Model -- a Mathematical model to capture the issues of resource management within multisession AMSs. In this model, each session provides a quality profile, which is a set of operating qualities arranged from the minimum acceptable quality to the maximum desired quality. Any operating quality may be mapped to the required resources using a quality-resource mapping, and also to a session utility using a quality-utility mapping. The main problem in a multisession AMS is to find an operating quality for each session such that the overall system utility (e.g. system revenue) is maximized under the system resource constraints. This is called the adaptive multimedia problem (AMP). The Utility Model formulates the AMP as the multiple-choice multi-dimension 0–1 knapsack problem (MMKP). It provides a unified and computationally feasible way to solve the admission problem for new multimedia sessions. and the dynamic quality adaptation and integrated resource allocation problems for existing sessions. In order to use the Utility Model, we propose two solutions for the (MMKP): a branch and bound algorithm BBLP for optimal solutions, and a heuristic HEU for fast and near-optimal solutions. We report computational experiences, and compare the two approaches for practical applications, finding that HEU solutions are usually within 4% of the optimum but at a much reduced computational cost. The heuristic HEU is suitable for time-critical applications such as real-time admission and adaptation decisions in multimedia systems. We present the Padma Architecture—a system architecture for multisession AMSs. This architecture has two novelties: (1) integrated and adaptive management of system resources based on the Utility Model, and (2) the use of metaspaces to encapsulate the machinery of quality adaptation. The former provides improved resource utilization and dynamic quality adaptation, and the latter provides the application programmers freedom from the concerns of low-level resource management issues while developing multimedia applications. Finally, we present the Utility Model Demonstration Prototype (UMDP)—a prototype which demonstrates the capability of the Utility Model to handle admission control, quality adaptation and integrated resource allocation in a unified way. We evaluate the performance of UMDP using random sequences of events, and show that the system utility achieved by the UMDP is significantly higher than that of a simple reservation model prototype (SRMP). For applications such multimedia service providers, it means that UMDP will generate more revenue than SRMP from the same amounts of system resources provisioned. / Graduate

Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 115-116).

published_or_final_version / Computer Science / Doctoral / Doctor of Philosophy

published_or_final_version / Computer Science and Information Systems / Doctoral / Doctor of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

In order to achieve superior speed in sequencer designs over competing PLD devices, Cypress brought to market an innovative architecture, CY7C361. This architecture introduced a new kind of universal logic gate, the CONDITION DECODER (CDEC). Because there are only 32 macrocells in the chip, saving only one CDEC gate can be quite important (the well-known "fit/no-fit problem"). A problem that is related to the fitting problem of the Cypress CY7C361 chip is the SOC Minimization. Due to the limited low number of macrocells in CY7C361, a high quality logic minimization to reduce the number of macrocells is very important. The goal of this thesis is, however, more general, since we believe that CDEC can be used as a generalpurpose gate for standard cell structures with few levels, and also for new PLD structures. We depart, therefore, from the Cypress chip as a sole motivation of our work, and we present a generic logic synthesis problem of SOC minimization. In this thesis, we formulate the SOC minimization problem and present a new kind of approach using graph coloring to solve it. A Cube Splitting algorithm is also presented, whereby the input cubes are split in such a way, that the generated cubes are lower in number than the minterms, and when these cubes are used as nodes in graph coloring algorithm, gives near exact solutions. The algorithms used in the SOC minimization program, SOCMIN, have been designed for Strongly Unspecified functions, defined by ON and OFF sets, and hence finds important applications for Machine Learning and Pattern theory, where there is a high percent of don't cares. The approach to solving the covering problem, the Conditional Graph Coloring, can be used in other similar problems such as PLA minimization, or Column Minimization Problem in Curtis-like decomposition of Multi-valued Relations. We found also the Muller method very efficient for ON,OFF data representation: it can be used to extend any other single-output minimizer for incomplete functions to a multi-output one.

Modular multiplication is a mathematical operation fundamental to the RSA cryptosystern, a public-key cryptosystem with many applications in privacy, security, and authenticity. However, cryptosecurity requires that the numbers involved be extremely large, typically ranging from 512-1024 bits in length. Calculations on numbers of this magnitude are cumbersome and lengthy; this limits the speed of RSA. This thesis examines the problem of speeding up modular multiplication of large numbers in hardware, using the classical (add-and-shift) multiplication algorithm. The problem is broken down, and it is shown that the primary computational bottleneck occurs in the modular reduction step performed on each cycle. This reduction consists of an integer division step, a broadcast step, and a multiplication step. Various methods of speeding up these steps are examined, both for the special case of radix-2 multipliers (those shifting a single bit at a time) and the general case of radix-2r multipliers (those shifting r bits on every cycle.) The impacts of these techniques, both on cycle time and on chip area, are discussed. The scalability of these systems is examined, and several implementations of modular multiplication found in the literature are analyzed. Most significantly, the technique of pipelining of modular multipliers is examined. It is shown that it is possible to pipeline the modular reduction sequence, effectively eliminating the cycle time's dependence on either the size of the modulus, or on the size of the radius. Furthermore, a technique for constructing such multipliers is given. It is demonstrated that this technique is scalable with respect to time, and that pipelining eliminates many of the disadvantages inherent in previous high-radix implementations. It is also demonstrated that such multipliers have an area requirement which is linear with respect to both radix and modulus size. / Graduation date: 1995