Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Allen R. Tannenbaum, Committee Member ; Jeffrey A. Davis, Committee Member ; Hsien-Hsin S. Lee, Committee Member ; Linda M. Wills, Committee Co-Chair ; D. Scott Wills, Committee Chair ; Gabriel H. Loh, Committee Member.

Thesis (M.S.)--Oregon Graduate Center, 1987.

Modern-day workloads, particularly those in big data, are heavily memory-latency bound. This is because of both irregular memory accesses, which have no discernable pattern in their memory addresses, and large data sets that cannot fit in any cache. However, this need not be a barrier to high performance. With some data structure knowledge it is typically possible to bring data into the fast on-chip memory caches early, so that it is already available by the time it needs to be accessed. This thesis makes three contributions. I first contribute an automated software prefetching compiler technique to insert high-performance prefetches into program code to bring data into the cache early, achieving 1.3x geometric mean speedup on the most complex processors, and 2.7x on the simplest. I also provide an analysis of when and why this is likely to be successful, which data structures to target, and how to schedule software prefetches well. Then I introduce a hardware solution, the configurable graph prefetcher. This uses the example of breadth-first search on graph workloads to motivate how a hardware prefetcher armed with data-structure knowledge can avoid the instruction overheads, inflexibility and limited latency tolerance of software prefetching. The configurable graph prefetcher sits at the L1 cache and observes memory accesses, which can be configured by a programmer to be aware of a limited number of different data access patterns, achieving 2.3x geometric mean speedup on graph workloads on an out-of-order core. My final contribution extends the hardware used for the configurable graph prefetcher to make an event-triggered programmable prefetcher, using a set of a set of very small micro-controller-sized programmable prefetch units (PPUs) to cover a wide set of workloads. I do this by developing a highly parallel programming model that can be used to issue prefetches, thus allowing high-throughput prefetching with low power and area overheads of only around 3%, and a 3x geometric mean speedup for a variety of memory-bound applications. To facilitate its use, I then develop compiler techniques to help automate the process of targeting the programmable prefetcher. These provide a variety of tradeoffs from easiest to use to best performance.

Software mobile agents is a new distributed computing paradigm which was developed to support efficient computing over the Internet. Since its inception there has been a significant research effort to produce concrete agent-based artefacts. This phenomenon resulted in the proliferation of a large number of agent systems, mostly based on proprietary programming languages, each with its own characteristics, peculiarities and assumptions. Hence the agent technology has largely remained hidden and incomprehensible by Internet end users. Moreover the issue of interoperability and integration of agents with existing legacy software has only just started to be addressed by the agent research community in a rather ad hoc way. In this thesis we attempt to design an agent architecture which is independent of any programming language and therefore is directly suitable for Internet end users. The proposed architecture, labelled as Mobile Agent System for Internet Computing (MASIC), addresses several important contemporary issues in agent research. It defines an agent as a container of reusable components that can be copied or moved to other agents. Each agent has a symmetric I/O access control module and is also equipped with associative access collaboration facilities. Additionally every agent contains a navigator module which stores the agent's itinerary plan and provides an interface via which the agent itself or other authorised agents can dynamically adapt the plan to reflect run-time events and constraints. The agent system provides an integrated access control architecture which enables an agent to define customised access control structures that can be fully or partially shared with other agents. Existing access control structures can be combined to create new structures that represent more complex access mechanisms. Agents can discover other agents offering pertinent services via an adaptive, customisable agent discovery architecture incorporated in MASIC. This discovery architecture enables the full interaction of links with queries and supports the definition of access paths which are tightly coupled with access control and. other customised services. MASIC also provides the conceptual architecture of a message-oriented agent communication system integrated with a mobility management scheme. Finally, this thesis presents the design and implementation of a prototype graphical interface which enables the potential user of the system to create, manage and interact with agents in real time. In conclusion the research presented in this thesis aims to provide a comprehensive, language-neutral, secure, collaborative environment within which mobile agents can interact with their peers in order to perform their tasks efficiently while human operators can oversee and manage these activities through a user friendly interface. The architecture is generic in nature as it can support general-purpose, agent-based computations. Its concepts, entities and mechanisms can be fully or partially re-used to provide architectural solutions to challenges in various application domains such as Knowledge Management, the GRID and E-Commerce.

No description available.

Almost all recent microprocessors and DSP chips perform addition, subtraction, multiplication and division in hardware. However, studying their performance reveals that division is not carried out as fast as the other three operations. One investigation shows that while floating-point division, with about 3 % of the dynamic floating - point instruction count, seems to be a relatively unimportant instruction, it may cause about 40 % degradation to the overall system performance. Several mathematical algorithms have been developed over the past 50 years to perform division quickly, with high precision. However, only a few are suitable for implementation in VLSI. Among them, digit recurrence algorithms are the most widely accepted methods of performing floating - point division in the latest processors. A survey shows that out of 13 recent processors, 11 use SRT division ¹ for performing floating - point division. Investigations show that SRT division gives the best tradeoff between delay and area. Selecting SRT division for implementing floating - point division is a reasonable choice because, unlike the other class of division algorithms, i.e. functional, it produces a correctly rounded quotient conforming to the IEEE 754 standard. There are techniques for improving the performance of SRT division. Of these, increasing the speed of quotient digit selection ( QDS ), making the best balance between the radix and the redundancy factor, representing the partial remainder in a redundant form, converting the quotient from redundant to conventional form the on - the - fly and overlapping the division recurrence components are the most important. In this thesis a different method of implementing the QDS function is proposed. This approach, which is described mathematically and architecturally, is based on the new comparison multiples idea. Unlike the traditional implementation of the QDS function, which searches for the quotient digit in a lookup table, the proposed method calculates the quotient digit directly in sign and magnitude format. This approach almost halves the fan out of some critical path components, which therefore operate faster. Having received the truncated partial remainder, the QDS function compares it with truncated multiples of the divisor to find the range in which the partial remainder belongs. The results of the comparisons are converted to the magnitude of the quotient digit using simple logic called the coder. Concurrently, another circuit checks the truncated partial remainder to determine whether the quotient digit is negative. This circuit operates off the critical path since the comparison multiples based QDS function calculates the sign and magnitude of the quotient digit separately. Having applied these changes, a faster QDS function and consequently, a shorter critical path delay for the floating - point divider is obtained. Implementations of radix - 4 and radix - 16 floating - point dividers are investigated and optimised to further decrease the cycle time. The idea of comparison multiples is extended to radix 10 to implement a decimal floating - point divider complying with the IEEE 754R standard. To achieve this goal, decimal signed - digit arithmetic along with implementations of carry - free addition and subtraction are proposed. The original comparison multiples based implementation of high - radix SRT division is modified to suit radix 10. The binary and decimal implementations of comparison multiples based division are evaluated for delay. Using the method of logical effort, the radix - 4, radix - 16 and decimal floating - point dividers are found to be faster than corresponding circuits reported in the public literature. Note : ¹ SRT division is a type of non - restoring digit recurrence division. / Thesis (Ph.D.)--School of Electrical and Electronic Engineering, 2005.

Thesis (M.S.)--University of Missouri--Rolla, 2007. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed April 22, 2008) Includes bibliographical references (p. 70-71).

No description available.

One of the main purposes of a Hastily Formed Network (HFN) is to provide immediate access to networked voice, data, and video services for as many users as possible. Following terrorist attacks like those in September 2001 or devastating natural disasters like the December 2004 Indian Ocean Tsunami and Hurricane Katrina in August 2005 users of the HFN will likely include survivors; first responders; local, state, and federal government agencies; non-government organizations; militaries; and others. These varied users will have different purposes for accessing HFN services; some will require their information to remain private while others will not. These needs for privacy and openness appear to present conflicting requirements: provide unrestricted access for many users but ensure â privacyâ or security of at least some information within the network. The purpose of this thesis is three-fold: first, to explore methodologies for securing the HFN; second, to examine commercial off-the-shelf (COTS) products and accepted best practices that provide the necessary security; and third, to provide a limited implementation example and a more robust target architecture that could provide security on the wireless segments while maintaining open access to the HFN and minimizing installation, operation, and maintenance complexity.

The Free Electron Laser (FEL) and Rail Gun are electric weapons which will require a significant amount of stored energy for operation. These types of weapons are ideal for use onboard an all-electric ship. An investigation is made of the effects these weapons will have on a proposed electrical system architecture using simulation modeling. Specifically, this thesis identifies possible design weaknesses and shows where further research and modeling is needed in order to ensure the proper integration of these electric weapons onboard an all-electric ship. The integration of these electric weapon systems with the power systems on electric ships will have an impact on naval operations. Several scenarios concerning specific naval missions are investigated using simulation software to understand the impact and limitations on the electric system using these new electric weapons.