The author proposes an architecture based on the Dynamic Actor Layer and the Game Manager in Delta3D to create a Networked Virtual Environment which could be used to train Navy Officers in tactics, allowing team training and doctrine rehearsal. The developed architecture is based on Object Oriented and Modular Design principles, while it explores the flexibility and strength of the Game Manager features in Delta3D game engine. The implementation of the proposed architecture is planned to be done in standard personal computers running's WindowsTM OS, but as Delta3D is a multiplatform tool, the generated code can be easily ported to Linux or even MacTM platforms. The designed architecture includes also a proposal for fast scenario creation and modification based on XML technology.

Fleet maneuvers, or division tactics (DIVTACS), are achieved by a series of precision shipboard movements directed by an Officer in Tactical Control. Much like a precision drill team, DIVTACS training requires multiple ships underway in close proximity, often a rare commodity. Costs to conduct live training range from several Thousand (per evolution) to several Million dollars (to repair ships after a collision at-sea). Computer simulation opens the door to maximizing DIVTACS training, while mitigating risk. The Navy spends in excess of 60 Million dollars per year on simulation-based training. Currently available simulators provide a DIVTACS capability by connecting several simulators together via a LAN. These simulators are cost prohibitive ranging from 1,00,000 dollars to Millions of dollars per unit. They are manpower and maintenance intensive requiring dedicated infrastructures, drastically limiting deploy-ability and reliability. Open source applications are gaining considerable leverage in the commercial market and offer significant cost-reductions. This thesis explored the possibilities of open source development by providing a proof of concept division tactics simulator. Additional considerations were given to the extension of the simulator for use in surface tactics in general and areas of future research.

Title: Efficient visibility calculation for light transport simulation in participating media Author: Čestmír Houška Department / Institute: Department of Software and Computer Science Educa- tion Supervisor of the master thesis: doc. Ing. Jaroslav Křivánek, Ph.D. Abstract: This thesis investigates the use of acceleration methods for the testing of visibility in light transport calculation algorithms with the emphasis on conser- vativeness and low accelerated query overhead. Several published non-directional and directional distance field methods are presented with the description of their characteristic properties. Two of these methods are then implemented and thor- oughly tested in an existing rendering framework on a path tracing volumetric integrator as well as on an own implementation of a ray marching single scattering integrator. A method that further accelerates the original distance field methods by pre-caching results of some of the queries is also proposed, implemented and tested. Furthermore, several possible extensions to this method are outlined. Keywords: computer graphics, rendering, participating media, visibility

This master thesis investigates and evaluates how a temporal component can help anti-aliasing with reduction of general spatial aliasing, preservation of thin geometry and how to get temporal stability in dynamic computer generated worlds. Of spatial aliasing, geometric aliasing is in focus but shading aliasing will also be discussed. Two temporal approaches are proposed. One of the methods utilizes the previous frame while the other method uses four previous frames. In order to do this an efficient way of re-projecting pixels are needed so this thesis deals with that problem and its consequences as well. Further, the results show that the way of taking and accumulating samples in these proposed methods show improvements that would not have been affordable without the temporal component for real-time applications. Thin geometry is preserved up to a degree but the proposed methods do not solve this problem for the general case. The temporal methods' image quality are evaluated against conventional anti-aliasing methods subjectively, by a survey, and objectively, by a numerical method not found elsewhere in anti-aliasing reports. Performance and memory consumption are also evaluated. The evaluation suggests that a temporal component for anti-aliasing can play an important role in increasing image quality and temporal stability without having a substantial negative impact of the performance with less memory consumed.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1980. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH. / Includes bibliographical references (leaves 75-76). / This report documents the initial development of a computer-controlled system for the production of three-dimensional forms. The project involved the design and construction of a carving device which was attached to an existing x-y plotter. The carving device was connected to a computer graphics system and various ways of using that system for three-dimensional design were explored. The material being carved is styrene foam in blocks, 4' x 4' x 1'. These carved blocks have potential use as sketches in exploring sculptural form, or as molds for the production of works in concrete fiberglass, or metal. / by Robert Faught. / M.S.

Thesis (M.S.V.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH. / Includes bibliographical references (leaves 298-306). / Posters are public inscriptions with strong roots in the development of graphic technology. They play an integral role in the development of graphic design. Current ideas about poster design are discussed to establish why and how recent technological possibilities may change our concept of the poster or alter the poster design process. Exercises in poster design using recent technological advances provide a demonstration of the nature of these changes and the potential they suggest. / by Nathan Immanuel Felde. / M.S.V.S.

Thesis (M.S.V.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1980. / Includes bibliographical references. / Three-dimensional, six degree of freedom input is explored in an interactive computer graphics environment. A particular device, the ROPAMS of Polhemus Navigational Sciences, Inc. is an accurate, unencumbering device based on electromagnetics. It is evaluated as a three-dimensional input device, and such input itself is evaluated for appropriateness and interactivity in a graphics environment. Emphasis is placed on human factors (pointing, body position) as a mode of interactivity. / by Christopher Schmandt. / Thesis (M.S.V.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1980.

Deformation of terrain is a natural component in real life. A car driving over a muddy area creates deep trails as the mud gives room to the tires. A person running across a snow-covered field causes the snow to deform to the shape of the feet. However, when these types of interactions between terrain and objects are modelled and rendered in real-time computer graphics applications, cheap approximations such as texture splatting is commonly used. This lack of realism not only looks poor to the viewer, it can also cause information to get lost and be a barrier to immersion. This thesis proposes an efficient system for permanent terrain deformations in real-time. In a volume-preserving manner, the ground material is displaced and animated as objects of arbitrary shapes intersect the terrain. Recent features of GPUs are taken advantage of to achieve high enough performance for the system to be used in real-time applications such as games and simulators.

A study on using colors to represent the floating population of tourists and local residents on the map by each hour in each month. The resulting visualization can assist the decision-making in various areas by providing a vivid description of the movement of people in a day.

by Hui Chau Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1991. / Includes bibliographical references. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.ii / TABLE OF CONTENTS --- p.iii / Chapter CHAPTER 1 --- INTRODUCTION / Chapter 1.1 --- Computer Graphics Today --- p.2 / Chapter 1.1.1 --- 3D Graphics Synthesis Techniques --- p.2 / Chapter 1.1.2 --- Hardware-assisted Computer Graphics --- p.4 / Chapter 1.2 --- About The Thesis --- p.5 / Chapter CHAPTER 2 --- GRAPHICS SYSTEM ARCHITECTURES / Chapter 2.1 --- Basic Structure of a Graphics Subsystem --- p.8 / Chapter 2.2 --- VLSI Graphics Chips --- p.9 / Chapter 2.2.1 --- The CRT Controllers --- p.10 / Chapter 2.2.2 --- The VLSI Graphics Processors --- p.11 / Chapter 2.2.3 --- Design Philosophies for VLSI Graphics Processors --- p.12 / Chapter 2.3 --- Graphics Boards --- p.14 / Chapter 2.3.1 --- The ARTIST 10 Graphics Controller --- p.14 / Chapter 2.3.2 --- The MATROX PG-1281 Graphics Controller --- p.16 / Chapter 2.4 --- High-end Graphics System Architectures --- p.17 / Chapter 2.4.1 --- Graphics Accelerator with Multiple Functional Units --- p.18 / Chapter 2.4.2 --- Parallel Processing Graphics Systems --- p.18 / Chapter 2.4.3 --- The Parallel Processor Architecture --- p.19 / Chapter 2.4.4 --- The Pipelined Architecture --- p.21 / Chapter 2.5 --- Comparisons and Discussions --- p.22 / Chapter 2.5.1 --- Parallel Processors versus Pipelined Processing --- p.23 / Chapter 2.5.2 --- Parallel Processors versus Multiple Functional Units --- p.23 / Chapter 2.6 --- Summary of High-end Graphics Systems --- p.24 / Chapter CHAPTER 3 --- AN ISA 3D GRAPHICS DISPLAY SERVER / Chapter 3.1 --- Common ISA Graphics Cards --- p.26 / Chapter 3.1.1 --- Standard Video Display Cards --- p.26 / Chapter 3.1.2 --- Graphics Processing Boards --- p.27 / Chapter 3.2 --- A Depth Processor for the ISA computers --- p.28 / Chapter 3.2.1 --- The Z-buffer Algorithm for HLHSR --- p.28 / Chapter 3.2.2 --- Our Hardware Solution for HLHSR --- p.29 / Chapter 3.2.3 --- Design of the Depth Processor --- p.31 / Chapter 3.2.4 --- Structure of the Depth Processor --- p.34 / Chapter 3.2.5 --- The Depth Processor Operations --- p.35 / Chapter 3.2.6 --- Software Support --- p.40 / Chapter 3.2.7 --- Performance of the Depth Processor --- p.44 / Chapter 3.3 --- A VGA Accelerator for the ISA Computers --- p.45 / Chapter 3.3.1 --- Display Buffer Structure of the SuperVGA --- p.46 / Chapter 3.3.2 --- Design of the VGA Accelerator --- p.47 / Chapter 3.3.3 --- Structure of the VGA Accelerator --- p.49 / Chapter 3.3.4 --- Combining the VGA Accelerator and the Depth Processor --- p.51 / Chapter 3.3.5 --- Actual Performance of the DP-VA Board --- p.54 / Chapter 3.3.6 --- 3D Graphics Applications Using the DP-VA Board --- p.55 / Chapter 3.4 --- A 3D Graphics Display Server --- p.57 / Chapter 3.5 --- Host Connection for the 3D Graphics Display Server --- p.59 / Chapter 3.5.1 --- The Single Board Computers --- p.60 / Chapter 3.5.2 --- The VME-to-ISA bus convenor --- p.61 / Chapter 3.5.3 --- Structure of the VME-to-ISA Bus Convertor --- p.61 / Chapter 3.5.4 --- Communications through the bus convertor --- p.64 / Chapter 3.6 --- Physical Construction of the DP-VA Board and the Bus Convertor --- p.65 / Chapter 3.7 --- Summary --- p.66 / Chapter CHAPTER 4 --- A MULTI-i860 3D GRAPHICS SYSTEM / Chapter 4.1 --- The i860 Processor --- p.69 / Chapter 4.2 --- Design of a Multiprocessor 3D Graphics System --- p.70 / Chapter 4.2.1 --- A Reconfigurable Processor-Pipeline System --- p.72 / Chapter 4.2.2 --- The Depth-Processing Unit --- p.73 / Chapter 4.2.3 --- A Multiprocessor Graphics System --- p.75 / Chapter 4.3 --- Structure of the Multi-i860 3D --- p.77 / Chapter 4.3.1 --- The 64-bit-wide Global Data Buses --- p.77 / Chapter 4.3.2 --- The 1280x1024 True-colour Display Unit --- p.79 / Chapter 4.3.3 --- The Depth Processing Unit --- p.82 / Chapter 4.3.4 --- The i860 Processing Units --- p.84 / Chapter 4.3.5 --- The System Control Unit --- p.87 / Chapter 4.3.6 --- Performance Prediction --- p.89 / Chapter 4.4 --- Summary --- p.90 / Chapter CHAPTER 5 --- CONCLUSIONS / Chapter 5.1 --- The 3D Graphics Synthesis Pipeline ……… --- p.91 / Chapter 5.2 --- 3D Graphics Hardware --- p.91 / Chapter 5.3 --- Design Approach for the ISA 3D Graphics Display Server --- p.92 / Chapter 5.4 --- Flexibility in the Multi-i860 3D Graphics System --- p.93 / Chapter 5.5 --- Future Work --- p.94 / Chapter APPENDIX A --- DISPLAYING REALISTIC 3D SCENES / Chapter A.1 --- Modelling 3D Objects in Boundary Representation --- p.96 / Chapter A.2 --- Transformations of 3D scenes --- p.98 / Chapter A.2.1 --- Composite Modelling Transformation --- p.98 / Chapter A.2.2 --- Viewing Transformations --- p.99 / Chapter A.2.3 --- Projection --- p.102 / Chapter A.2.4 --- Window to Viewport Mapping --- p.104 / Chapter A.3 --- Implementation of the Viewing Pipeline --- p.105 / Chapter A.3.1 --- Defining the View Volume --- p.105 / Chapter A.3.2 --- Normalization of The View Volume --- p.106 / Chapter A.3.3 --- The Overall Transformation Pipeline --- p.108 / Chapter A.4 --- Rendering Realistic 3D Scenes --- p.108 / Chapter A.4.1 --- Scan-conversion of Lines and Polygons --- p.108 / Chapter A.4.2 --- Hidden Surface Removal --- p.109 / Chapter A.4.3 --- Shading --- p.112 / Chapter A.4.4 --- The Complete 3D Graphics Pipeline --- p.114 / Chapter APPENDIX B --- DEPTH PROCESSOR DESIGN DETAILS / Chapter B.l --- PAL Definitions --- p.116 / Chapter B.2 --- Circuit Diagrams --- p.118 / Chapter B.3 --- Depth Processor User's Guide --- p.121 / Chapter APPENDIX C --- VGA ACCELERATOR DESIGN DETAILS / Chapter C.1 --- PAL Definitions --- p.124 / Chapter C.2 --- Circuit Diagram --- p.125 / Chapter C.3 --- The DP-VA User's Guide --- p.127 / Chapter APPENDIX D --- VME-TO-ISA BUS CONVERTOR DESIGN DETAILS / Chapter D.1 --- PAL Definitions --- p.131 / Chapter D.2 --- Circuit Diagrams --- p.133 / Chapter APPENDIX E --- 3D GRAPHICS LIBRARY ROUTINES FOR THE DP-VA BOARD / Chapter E.1 --- 3D Drawing Routines --- p.136 / Chapter E.2 --- 3D Transformation Routines --- p.137 / Chapter E.3 --- Shading Routines --- p.138 / Chapter APPENDIX F --- PIPELINE CONFIGURATIONS FOR N PROCESSORS / REFERENCES