Thesis (Ph. D.)--University of Hong Kong, 2007. / Title proper from title frame. Also available in printed format.

The research we have conducted has been aimed at developing a new mechanism of extraction and use of parallelism at a high level, based on speculation techniques, in cluster environments. This allows our mechanism to be architecture independent and to be adapted to heterogeneous environments. As a drawback there are some limitations due to the fact of working at a high level, such as memory address access dependencies and those occurring in vector operations. The Master/Slave Speculative Parallelization Architecture for Computer Clusters (MSSPACC) is considered that works at the TLP taking advantage of the execution tools of the ILP level. It works at TLP level because the program is divided into threads which we call blocks. The blocks they are considered like single instructions and follow the same pattern of a superscalar processor ILP (input variables are considered like operands and the output like the result of the execution). / L’objectiu d’aquesta recerca és desenvolupar un nou mecanisme d'extracció i explotació del paral•lelisme basat en tècniques d'especulació a nivell d’aplicació sobre clústers. Així hem aconseguit que el sistema no tingui una dependència arquitectònica i poder adaptar-se a entorns heterogenis. Com a contrapartida ens hem trobat amb les limitacions degudes al fet de treballar a nivell d’aplicació, com són les dependències d’adreces d’accés a memòria i les provocades en operacions amb vectors. La proposta desenvolupada s’anomena Master/Slave Speculative Parallelization Architecture for Computer Clusters (MSSPACC) i es pot considerar que treballa a nivell TLP aprofitant les eines d’execució del nivell ILP. Divideix el programa en fils d’execució que anomenem blocs bàsics que s’executen seguint el mateix patró ILP d’un processador Superescalar, considerant que un bloc bàsic és equivalent a una instrucció, les variables d’entrada com a operants i les de sortida com al resultat de l’execució del bloc bàsic.

Delay tolerant networks (DTNs) are a class of emerging networks that exhibit significantly different characteristics from today's Internet, such as intermittent connectivity, large delay, and high loss rates. DTNs have important applications in disaster relief, military, rural Internet access, environmental sensing and surveillance, interplanetary communication, underwater sensing, and vehicular communication. While not the common case for networking, DTNs represent some of the most critical cases, where the ability to communicate can make a huge difference for human lives. Supporting effective communication in DTNs, however, is challenging. First, with intermittent connectivity, DTNs are often extremely limited in capacity. Second, given resource limitations and uncertainty in DTNs, it is critical to deliver data efficiently and robustly. The situation is especially acute for multicast which sends data to multiple destinations. This thesis seeks to address these two issues. To enhance network capacity in DTNs, we propose a message ferrying scheme that exploits the use of special mobile nodes (called message ferries) and controlled device mobility to deliver data. Message ferries are utilized to transport data via mobility between sources and destinations. We develop a foundation for the control of the mobility of message ferries, and nodes if possible, to cooperatively deliver data under a variety of conditions. We also study another approach which deploys new nodes called throwboxes to enhance capacity. Throwboxes are small and inexpensive wireless devices. By relaying data between mobile nodes, throwboxes are able to create data transfer opportunities that otherwise would not exist. We systematically investigate the issues of deployment and routing, and develop algorithms for various deployment and routing approaches. Based on extensive evaluation, we obtain several findings to guide the design and operation of throwbox-augmented DTNs. To address the issue of efficient and robust data delivery, we focus on DTN multicasting. Given the unique characteristics of DTNs, traditional solutions such as IP multicast can not be simply ported to DTNs. We identify the limitations of IP multicast semantics in DTNs and define new semantic models for DTN multicast. Based on these semantic models, we develop and evaluate several multicast routing algorithms with different routing strategies.

Overlay networks have recently gained popularity as a viable alternative to overcome functionality limitations of the Internet (e.g., lack of QoS, multicast routing). They offer enhanced functionality to end-users by forming an independent and customizable virtual network over the native network. Typically, the routing at the overlay layer operates independent of that at the underlying native layer. There are several potential problems with this approach because overlay networks are selfish entities that are chiefly concerned with achieving the routing objective of their own users. This leads to complex cross-layer interactions between the native and overlay layers, and often tends to degrade the achieved performance for both layers. As overlay applications proliferate and the amount of selfish overlay traffic surges, there is a clear need for understanding the complex interactions and for strategies to manage them appropriately. Our work addresses these issues in the context of "service overlay networks", which represent virtual networks formed of persistent nodes that collaborate to offer improved services to actual end-systems. Typically, service overlays alter the route between the overlay nodes in a dynamic manner in order to satisfy a selfish objective. The objective of this thesis is to improve the stability and performance of overlay routing in this multi-layer environment. <br><br> We investigate the common problems of functionality overlap, lack of cross-layer awareness, mismatch or misalignment in routing objectives and the contention for native resources between the two layers. These problems often lead to deterioration in performance for the end-users. This thesis presents an analysis of the cross-layer interaction during fault recovery, inter-domain policy enforcement and traffic engineering in the multi-layer context. Based on our characterization of the interaction, we propose effective strategies that improve overall routing performance, with minimal side-effects on other traffic. These strategies typically 1) increase the layer-awareness (awareness of information about the other layer) at each layer, 2) introduce better control over routing dynamics and 3) offer improved overlay node placement options. Our results demonstrate how applying these strategies lead to better management of the cross-layer interaction, which in turn leads to improved routing performance for end-users.

The objective of this research is to develop an optimized quality of service (QoS) assurance algorithm with the differentiated services (DiffServ) architecture, and a differentiated polling algorithm with efficient bandwidth allocation for QoS assurance in the hybrid multi-hop mesh/relay networks. These wide area networks (WANs), which will employ a connection-based MAC protocol, along with QoS-enabled wireless local area networks (WLANs) that use a contention-based MAC protocol, need to provide an end-to-end QoS guarantee for data communications, particularly QoS-sensitive multimedia communications. Due to the high cost of construction and maintenance of infrastructure in wireless networks, engineers and researchers have focused their investigations on wireless mesh/relay networks with lower cost and high scalability. For current wireless multi-hop networks, an end-to-end QoS guarantee is an important functionality to add, because the demand for real-time multimedia communications has recently been increasing. For real-time multimedia communication in heterogeneous networks, hybrid multi-hop mesh/relay networks using a connection-based MAC protocol, along with QoS-enabled WLANs that use a contention-based MAC protocol can be an effective multi-hop network model , as opposed to multi-hop networks with a contention-based MAC protocol without a QoS mechanism. To provide integrated QoS support for different QoS mechanisms, the design of the cross-layer DiffServ architecture that can be applied in wireless multi-hop mesh/relay networks with WLANs is desirable. For parameterized QoS that requires a specific set of QoS parameters in hybrid multi-hop networks, an optimized QoS assurance algorithm with the DiffServ architecture is proposed here that supports end-to-end QoS through a QoS enhanced WAN for multimedia communications. For a QoS assurance algorithm that requires a minimum per-hop delay, the proper bandwidth to allow the per-hop delay constraint needs to be allocated. Therefore, a polling algorithm with a differentiated strategy at multi-hop routers is proposed here. The proposed polling algorithm at a router differentially computes and distributes the polling rates for routers according to the ratio of multimedia traffic to overall traffic, the number of traffic connections, and the type of polling service. By simulating the architecture and the algorithms proposed in this thesis and by analyzing traffic with the differentiated QoS requirement, it is shown here that the architecture and the algorithms produce an excellent end-to-end QoS guarantee.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

published_or_final_version / abstract / toc / Computer Science / Master / Master of Philosophy

Resource virtualization is emerging as a technology to enable the management and sharing of hardware resources including multiple core processors and accelerators such as Digital Signal Processors (DSP), Graphics Processing Units (GPU), and Field Programmable Gate Arrays (FPGA). Accelerators present unique problems for virtualization and sharing due to their specialized architectures and interaction modes. This thesis explores and proposes solutions for the virtualized operation of high performance, quality of service (QoS) packet scheduling accelerators. It specifically concentrates on challenges to meet 10Gbps Ethernet wire speeds. The packet scheduling accelerator is realized in a FPGA and implements the Sharestreams-V architecture. ShareStreams-V implements the Dynamic Window-Constrained Scheduler (DWCS) algorithm, and virtualizes the previous ShareStreams architecture. The original ShareStreams architecture, implemented on Xilinx Virtex-I and Virtex-II FPGAs, was able to schedule 128 streams at 10Gbps Ethernet throughput for 1500-byte packets. Sharestreams-V provides both hardware and software extensions to enable a single implementation to host isolated, independent virtual schedulers. Four methods for virtualization of the packet scheduler accelerator are presented: coarse- and fine-grained temporal partitioning, spatial partitioning, and dynamic spatial partitioning. In addition to increasing the utilization of the scheduler, the decision throughput of the physical scheduler can be increased when sharing the physical scheduler across multiple virtual schedulers among multiple processes. This leads to the hypothesis for this work: Virtualization of a quality of service packet scheduler accelerator through dynamic spatial partitioning is an effective and efficient approach to the accelerator virtualization supporting scalable decision throughput across multiple processes. ShareStreams-V was synthesized targeting a Xilinx Virtex-4 FPGA. While sharing among four processes, designs that supported up to 16, 32, and 64 total streams are able to reach 10Gbps Ethernet scheduling throughput for 64-byte packets. When sharing among 32 processes, a scheduler supporting 64 total streams was able to reach the same throughput. An access API presents the virtual scheduler abstraction to individual processes in order to allocate, deallocate, update and control virtual the scheduler allocated to a process. Practically, the bottleneck for the test system is the software to hardware interface. Effective future implementations are anticipated to use a tightly-coupled host CPU to accelerator interconnect.

Thesis (M.ICT.)--University of Wollongong, 2006. / Typescript. Includes bibliographical references: leaf 112-121.

Thesis (M.C.S.)--Carleton University, 2005. / Includes bibliographical references (p. 89-91). Also available in electronic format on the Internet.