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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
31

Charge-based analog circuits for reconfigurable smart sensory systems

Peng, Sheng-Yu. January 2008 (has links)
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
32

Incremental placement for modern VLSI design closure

Ren, Haoxing 28 August 2008 (has links)
Not available / text
33

Testing for delay defects utilizing test data compression techniques

Putman, Richard Dean, 1970- 29 August 2008 (has links)
As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways. / text
34

Analog-digital converter : strip chart to punched card.

Michalski, Joseph Eugene. January 1971 (has links)
No description available.
35

Test generation for fault isolation in analog and mixed-mode circuits

Chakrabarti, Sudip 05 1900 (has links)
No description available.
36

Part I, Computer-aided electronic circuit design : Part II, Thin-film active device investigations

January 1968 (has links)
Massachusetts Institute of Technology Electronic Systems Laboratory Department of Electrical Engineering. / Bibliography: p. 27-29. / NASA research grant NsG-496 M.I.T. Projects DSR 76152
37

Computer-aided electronic circuit design

January 1968 (has links)
Massachusetts Institute of Technology Electronic Systems Laboratory Department of Electrical Engineering. / Bibliography: p. 16-20. / NASA research grant NsG-496 M.I.T. Projects DSR 76152
38

Introduction to data communication

January 1983 (has links)
Pierre A. Humblet. / "January, 1983." Caption title. / Bibliography: leaves 9-10. / NSF Grant ECS 79-19880
39

Library Characterization and Static Timing Analysis of Single-Track Circuits in GasP

Mettala Gilla, Swetha 01 January 2010 (has links)
Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization with respect to asynchronous circuits, and ties the results into the STA solution of USC. The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and light in power. They have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP circuits excellent candidates for modern many-core, concurrent network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a `single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, the results of this work will provide confidence in the correct operation of GasP circuits.
40

Analog-digital converter : strip chart to punched card.

Michalski, Joseph Eugene. January 1971 (has links)
No description available.

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