A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. Seamless run-time reconfiguration requires rapid configuration. Commodity programmable devices have relatively long configuration time, which makes them poor candidates for run-time reconfigurable systems. Reducing this reconfiguration time to the order of nano seconds will enable rapid run-time reconfiguration. Having multiple configuration planes and switching between them while processing data is one approach towards achieving rapid reconfiguration. An experimental context switching programmable device, called the Context Switching Reconfigurable Computer (CSRC), has been created by BAE Systems, which provided opportunities to explore context-switching strategies for run-time reconfigurable systems. The work presented here studies this approach for run-time reconfiguration, by applying the concepts to develop applications on a context switching reconfigurable system. The work also discusses the advantages and disadvantages of such an approach and ways of leveraging the concept for efficient computing. / Master of Science

Broadband wireless technologies have the potential to provide integrated data and multimedia services in several niche areas. There is a growing need to develop high-performance communication systems that can satisfy high-end data processing requirements inherent in these technologies. The speed and complexity of these systems necessitates designers to break away from traditional architectures and design methodologies. A more comprehensive and demanding design and verification process including both hardware and software is required. Field-programmable gate arrays (FPGA) offer an attractive alternative to the low efficiency of Digital Signal Processor (DSP) based systems and low flexibility of Application Specific Integrated Circuits(ASIC). The availability of high-density, high-performance field-programmable gate arrays with several capabilities, like embedded memory and advanced routing, together with the adaptability that they offer make them highly desirable for developing hardware prototypes of communication systems. This thesis describes the development of a configurable architecture and FPGA-based design methodology used in the development of a Local Multipoint Distribution Service (LMDS) gateway for a disaster response network. The design of the gateway posed several challenges due to high data rates (120 Mbits/sec) and adaptive features like variable Forward Error Correction Coding and optional link-level retransmissions. The design decisions and simulation results of the verification process are discussed in detail. Finally, the aspects of testing and integration of the prototype in the overall system are discussed. / Master of Science

The growth of high performance computing to date can largely be attributed to continuing breakthroughs in materials and manufacturing.In order to increase computing capacity beyond these physical bounds, new computing paradigms must be developed that make more efficient use of existing manufacturing technologies. Custom Computing Machines (CCMs) are an emerging class of computers that offer promising possibilities for future high-performance computational needs. With the increasing popularity of the run-time reconfigurable (RTR) concept in the CCM community, questions have arisen as to what computational device should be at the heart of an RTR platform. Currently the preferred device, and really the only practical device, has been the RAM-based Field-Programmable Gate Array (FPGA). Unfortunately, for applications that require high performance, FPGAs are limited by their narrow data path and small computational density. The Colt integrated circuit has been designed from the start to be the computational processing element in an RTR platform. Colt is an RTR data-flow processor array with a course-grain architecture (16-bit data path). This thesis covers the VLSI implementation and verification of the Colt integrated circuit, including the approach and methods necessary to make a functionally working integrated circuit. / Master of Science

The wireless market of the future will demand inexpensive hardware, expandability, interoperability, and the implementation of advanced signal processing functions--i.e. a software radio. Configurable computing machines are often ideal software radio platforms. In particular, the Stallion reconfigurable processor's efficient hardware reuse and scalability fulfill these radios' demands. The advantages of Stallion-based design inspired an FPGA-based software radio - the proto-Stallion receiver. This thesis introduces the proto-Stallion architecture and details its implementation on the SLAAC-1V FPGA platform. Although this thesis presents a specific radio implementation, this architecture is flexible; it can support a variety of applications within its fixed framework. This implemented single-user DS-CDMA receiver utilizes an LMS adaptive filter that can combat MAI and constructively combine multipath; most notably, this receiver employs an adaptive tracking algorithm that harnesses the LMS algorithm to maintain symbol synchronization. The proto-Stallion receiver demonstrates the dependence of adaptive tracking on channel noise; the algorithm requires significant noise levels to maintain synchronization. / Master of Science

Research efforts have shown that capacity in a DS/CDMA cellular system can be increased through the use of digital signal processing techniques that exploit the nature of the multiple access interference (MAI). By jointly demodulating the users in the system, this interference can be characterized and reduced thus decreasing the overall probability of error in the system. Numerous multiuser structures exist, each with varying degrees of complexity and performance. However, the size and complexity of these structures is large relative to a conventional receiver. This effort demonstrates a practical approach to implementing parallel interference cancellation applied to DBPSK DS/CDMA on an FPGA-based configurable computing platform. The system presented acquires, tracks, cancels, and demodulates four users independently and performs various levels of interference cancellation. The performance gain of the receiver in a four-user environment under various levels of noise and cancellation are presented. / Master of Science

Embedded systems are becoming nearly ubiquitous, found in a plurality of devices ranging from everyday cars and dishwashers to sophisticated spy satellites and remote sensing equipment. As the applications for embedded systems increase in number and diversity and continue to pervade our lives, a need arises to secure these systems. Whether the need arises from a desire to protect personal, proprietary, sensitive, or classified information, the security of the embedded system seeks to maintain the confidentiality and integrity of data contained within the system. Research into securing embedded systems is in its nascent stages. The generally accepted methodology of securing embedded systems involves techniques that either modify an embedded system's processor or entail custom ASIC hardware. This thesis presents a novel embedded system architecture for secure software processing that does not involve processor modification, but rather processor augmentation to ensure the confidentiality and integrity of information contained within the embedded system. Specifically, configurable logic placed at the processor periphery provides just-in-time cryptographic transformation of instructions, data, and I/O of a running embedded application. In addition to presenting the embedded secure software platform, this thesis provides a characterization of the data protection architecture of the platform. / Master of Science

Configurable process models are integrated representations of multiple variants of a process model in a given domain, e.g. multiple variants of a shipment-to-delivery process in the logistics domain. Configurable process models provide a basis for managing variability and for enabling reuse of process models in Process-Aware Information Systems. Rather than designing process models from scratch, analysts can derive process models by configuring existing ones, thereby reusing proven practices. This thesis starts with the observation that existing approaches for capturing and managing configurable process models suffer from three shortcomings that affect their usability in practice. Firstly, configuration in existing approaches is performed manually and as such it is error-prone. In particular, analysts are left with the burden of ensuring the correctness of the individualized models. Secondly, existing approaches suffer from a lack of decision support for the selection of configuration alternatives. Consequently, stakeholders involved in the configuration of process models need to possess expertise both in the application domain and in the modeling language employed. This assumption represents an adoption obstacle in domains where users are unfamiliar with modeling notations. Finally, existing approaches for configurable process modeling are limited in scope to control-flow aspects, ignoring other equally important aspects of process models such as object flow and resource management. Following a design science research method, this thesis addresses the above shortcomings by proposing an integrated framework to manage the configuration of process models. The framework is grounded on three original and interrelated contributions: (i) a conceptual foundation for correctness-preserving configuration of process models; (ii) a questionnaire-driven approach for process model configuration, providing decision support and abstraction from modeling notations; (iii) a meta-model for configurable process models covering control-flow, data objects and resources. While the framework is language-independent, an embodiment of the framework in the context of a process modeling language used in practice is also developed in this thesis. The framework was formally defined and validated using four scenarios taken from different domains. Moreover, a comprehensive toolset was implemented to support the validation of the framework.

This thesis presents design, fabrication and testing of a number of multi-frequency band microstrip-fed re-configurable microstrip patch antennas. All re-configurable antennas are designed to change from one resonance frequency to another by an electronic control of RF MEMS switches, one at a time. Besides a fixed size slot on the patch, switches are placed in insets for satisfying better input match at each resonance frequency individually. Also some switches are placed into the slot for adding another resonance frequency to change the effective slot-length like effective inset length changing.To actuate the RF MEMS switches in the configured way, DC-stubs are also designed to apply required potential difference between switch ports and the carrier. These stubs exhibit RF-open at switch side to prevent any RF leakage, and DCground on the other side. That RF short-to-open conversion is accomplished together with feed structure / with a taper depending on the feed network selected. All devices introduced here are built by Microwave Research Group in Electrical and Electronics Department, Middle East Technical University. Depending on the sensitivity of structure, some devices are built by RF MEMS group in Microelectronic Production Plant for MEMS (METU &amp / #8211 / MET) during the thesis study. Therefore this study is the continuation of the first national work on fabrication of RF MEMS devices.

Robotics is an emerging field, and it is also affecting several other fields. Design of robotic platforms gains more importance since the focus and aim of the robotics research broadens widely and the variety of the users is significant. This work aims to present the design of a modular mobile robotic platform, which should be simple, easy to build and easy to use. The concept of modularity, usage of off-the shelf components and utilizing a PC platform, are addressed in this work. As a result of this work, a conceptual design is presented, and a prototype is built to highlight some important aspects of the conceptual design.

Esta dissertação propõe a utilização da técnica de filtragem adaptativa de pulsos transientes de modo a proteger os circuitos integrados sob efeito da radiação ionizante. Para garantir o uso desta técnica é necessária a utilização de um flip-flop tolerante à radiação que possua a capacidade de ter um ajuste de atraso configurável. O objetivo do uso do flip-flop programável é ter a opção de selecionar o atraso mais apropriado para filtragem temporal de pulsos de SET para cada circuito. Sendo assim, cada flip-flop pode filtrar SETs pelo uso de diferentes atrasos, baseado no atraso de propagação de cada caminho lógico. A variação nos atrasos de propagação entre múltiplos caminhos combinacionais pode ser usada para aumentar ou reduzir o atraso da filtragem de SET. Esta abordagem foi validada com o estudo de caso através de simulação elétrica e pela injeção de milhares de pulsos de SET com diferentes larguras em um circuito com filtragem adaptativa de pulsos tolerantes, os quais foram injetados de forma randômica no circuito. Os resultados mostraram o uso eficiente desta técnica de filtragem de SET em circuitos integrados. De modo a maximizar os resultados, um novo elemento de atraso programável foi desenvolvido e inserido no flip-flop. Para validação deste novo elemento, um segundo estudo de caso, utilizando o conjunto de circuitos dos benchmarks do ISCAS'85 foi também avaliado com a injeção de falhas. Os resultados mostraram que o uso do método proposto, reduz o número de erros sem perda de desempenho e com baixo incremento de área. / This dissertation proposes the use of an adaptive filtering technique of transient pulses in order to protect the integrated circuit under the effect of radiation. To ensure this technique it is necessary to use a tolerant radiation flip-flop having the ability to have a configurable delay adjustment. The purpose of the use a programmable radiation hardened flip-flop is having option of to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Thus, each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. This approach was validated in a case-study by electrical simulation with injection of thousands of SET pulses of different widths, which were randomly injected in a circuit with adaptive filtering technique and the results showed efficient use of this SET filtering technique in integrated circuits. In order to maximize the results of this technique a new programmable delay element was developed and inserted into the flip-flop. This approach of the new element was validated in a second case-study, using a set of benchmark circuits from ISCAS’85 was also evaluated by injecting faults. Results showed that using the proposed method, the number of errors can be reduced without decreasing the performance and with low area overhead.