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1	Analyse statique de l'effet des erreurs de configuration dans des FGPA configurés par SRAM et amélioration de robustesse / Modeling faults in SRAM based FPGA and appropriate protections Ferron, Jean-Baptiste 26 March 2012 (has links) Cette thèse s'intéresse en premier lieu à l'analyse des effetsfonctionnels des erreurs dans laconfiguration de FPGAs à base de SRAM. Ces erreurs peuvent provenir deperturbations naturelles(rayonnements, particules) ou d'attaques volontaires, par exemple avecun laser. La famille Virtex IIde Xilinx est utilisée comme premier cas pratique d'expérimentation,puis une comparaison est réaliséeavec la famille AT40K de chez ATMEL. Ceci a permis de mieux comprendrel'impact réel dedifférentes sources de perturbations, et les motifs d'erreur devantréellement être pris en compte pouraméliorer la robustesse d'un circuit implanté sur ce type detechnologie. Cette étude a nécessité ledéveloppement d'outils de conception spécifiques, permettantd'automatiser les analyses. Uneméthodologie innovante est proposée pour l'évaluation de lasensibilité de la mémoire de configurationaux SEUs : une classification des bits de configuration est établie enfonction des effets produits parleur inversion sur le fonctionnement normal de l'application. Cecipermet de déterminer les zones lesplus critiques, autorisant le développement de stratégies deprotection sélectives et à faible coût. / This thesis deals primarily with the analysis of the functionaleffects of errors in the configuration ofSRAM-based FPGAs. These errors can be due either to naturalperturbations (radiations, particles) orto malicious attacks, for example with a laser. The Xilinx Virtex IIfamily is used as first case study,then a comparison is made with the ATMEL AT40K family. This workallowed us a betterunderstanding of the real impact of perturbations, and of the errorpatterns that need to be taken intoaccount when improving the robustness of a circuit implemented on thistype of technology. Thisstudy required the development of specific design tools to automatethe analyses. An innovativemethodology is proposed for the evaluation of the configuration memorysensitivity to SEUs: aclassification of configuration bits is made with respect to theeffects produced on the application by asingle bit-flip. This enables us to identify the most critical areas,and to propose selective hardeningsolutions, improving the global reliability of the application at low cost. FPGAs SRAM Mémoire de configuration Analyse statique de criticité Robustesse FPGA SRAM Configuration memory Static analysis of criticality Reliability Single Event Upset
2	High-Speed Programmable FPGA Configuration Memory Access Using JTAG Gruwell, Ammon Bradley 01 April 2017 (has links) Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications. FPGA JTAG scrubbing fault injection radiation testing laser testing C++ Python BYU configuration readback reliability SEU Xilinx bitstream upset mitigation hardware software high speed configuration memory CRAM SRAM Joint Test Action Group ionizing radiation space aerospace interface serial ARM processor architecture programmable logic MicroZed Zynq Linux Electrical and Computer Engineering

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Analyse statique de l'effet des erreurs de configuration dans des FGPA configurés par SRAM et amélioration de robustesse / Modeling faults in SRAM based FPGA and appropriate protections

High-Speed Programmable FPGA Configuration Memory Access Using JTAG