Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

The scaling required to accommodate faster chip performance in microelectronic devices has necessitated a reduction in the dimensions of copper interconnects at the back end of the line. The constant downscaling of copper interconnects has resulted in changes to the microstructure, and these variations are known to impact electrical resistivity and reliability issues in interconnects. In this work, a novel electron diffraction technique called Diffraction Scanning Transmission Electron Microscopy (D-STEM) has been developed and coupled with precession electron microscopy to obtain quantitative local texture information in damascene copper lines (1.8 \mu m to 70 nm in width) with a spatial resolution of less than 5 nm. Misorientation and trace analysis has been performed to investigate the the grain boundary distribution in these lines. The results reveal strong variations in texture and grain boundary distribution of the copper lines upon downscaling. 1.8 \mu m wide lines exhibit strong <111> normal texture and comprise large bamboo-type grains. Upon downscaling to 180 nm, a {111} <110> biaxial texture has been observed. In contrast, narrower lines of widths 120 nm and 70 nm reveal sidewall growth of {111} grains and a dominant <110> normal texture. The fraction of coherent twin boundaries also reduces with decreasing line width. The microstructure changes from bamboo-type in wider lines to one comprising clusters of small grains separated by high angle boundaries in the vicinity of large grains. The evolution of such a microstructure has been discussed in terms of overall energy minimization and dimensional constraints. Finite element analysis has been performed to correlate misorientations between grains and local thermal stresses associated with stress migration. Effect of variations in the copper interconnect microstructure on electromigration flux divergence has also been discussed. / text

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C. / Singapore-MIT Alliance (SMA)

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate \((MnSi_xO_y)\) layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These \((MnSi_xO_y)\) layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride \((Mn_4N)\) layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the \(Mn_4N\) layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. \(Mn_4N\) is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process. / Chemistry and Chemical Biology

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.