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<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

Este trabalho apresenta o projeto de um conversor digital-analógico (DAC) para ser usado em um transmissor RF no padrão Bluetooth. Um DAC é usado em um transmissor RF por que os sinais processados digitalmente devem ser transmitidos analogicamente para outras estações de rádio. Nesta aplicação especificações do conversor como: frequência de amostragem, resolução, Faixa dinâmica livre de espúrios (SFDR), Relação sinal-ruído (SNR) e não-linearidade integral e diferencial (INL e DNL), são determinadas pelo padrão de modulação do transmissor RF que neste trabalho ´e Bluetooth. Além de baixo consumo de potência e de área, condições necessárias para implementar um sistema portável. A arquitetura current-steering segmentada é adequada para este tipo de aplicação. Esta arquitetura se baseia em um conjunto de fontes de corrente, as quais são comutadas para gerar uma tensão de saída. O projeto das fontes de corrente num DAC current steering determina o comportamento dinâmico e estático. No entanto, na literatura muitos trabalhos não têm uma boa estratégia de projeto. Como uma solução, este trabalho apresenta um estudo das variáveis e uma estratégia para o projeto de um DAC nesta arquitetura. A estratégia de projeto proposta para as fontes de corrente, consiste em um processo iterativo onde as variáveis são ajustadas de maneira simples, cumprindo os requerimentos, minimizando o consumo de potência e atingindo as especificações. Além disso, neste trabalho é incluída uma análise teórica dos requerimentos estáticos e dinâmicos, além de uma nova estratégia para a implementação do layout com a qual se obtém um baixo consumo de área. O DAC foi projeto e implementado em tecnologia CMOS de 0,35?m 4M2P. Alguns resultados obtidos no teste experimental são: área ativa do layout de 200?m×200?m, Corrente de escala completa de 700?A (uma tensão de alimentação de 3,3V), INL=0,3LSB, DNL=0,37LSB, SFDR=58dB para um sinal senoidal de saída de 1MHz e 50MHz de frequência de amostragem, SFDR=52dB para um sinal senoidal de saída de 1MHz e 10MHz de frequência de amostragem. / This work presents a digital-to-analog converter (DAC) design used in a RF transmitter stage for Bluetooth applications. A DAC is used in a RF transmitter because digitally processed signals must be transmitted as an analog wave to other radio stations. The DAC design must fulfill specifications of: sampling frequency, resolution, Spurious-Free Dynamic Range (SFDR), Signal-to-Noise Ratio (SNR) and Differential and Integral Nonlinearities (DNL, INL). These specifications are determined by the modulation standard of the RF transmission stage which in our work is Bluetooth. Also, low power and reduced area are required conditions to implement portable systems. Current-steering segmented architecture is suitable for this application [1]. It is based on an array of matched current sources that are switched to generate the output voltage. The Current sources design in a current steering DAC determines the converter\'s static and dynamic behavior. However, in the literature many works did not present a good design estrategy. As a solution, this work presents a study of the variables tradeoffs and a simple design strategy for current-steering segmented DAC design. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing.

Este trabalho apresenta o projeto de um conversor digital-analógico (DAC) para ser usado em um transmissor RF no padrão Bluetooth. Um DAC é usado em um transmissor RF por que os sinais processados digitalmente devem ser transmitidos analogicamente para outras estações de rádio. Nesta aplicação especificações do conversor como: frequência de amostragem, resolução, Faixa dinâmica livre de espúrios (SFDR), Relação sinal-ruído (SNR) e não-linearidade integral e diferencial (INL e DNL), são determinadas pelo padrão de modulação do transmissor RF que neste trabalho ´e Bluetooth. Além de baixo consumo de potência e de área, condições necessárias para implementar um sistema portável. A arquitetura current-steering segmentada é adequada para este tipo de aplicação. Esta arquitetura se baseia em um conjunto de fontes de corrente, as quais são comutadas para gerar uma tensão de saída. O projeto das fontes de corrente num DAC current steering determina o comportamento dinâmico e estático. No entanto, na literatura muitos trabalhos não têm uma boa estratégia de projeto. Como uma solução, este trabalho apresenta um estudo das variáveis e uma estratégia para o projeto de um DAC nesta arquitetura. A estratégia de projeto proposta para as fontes de corrente, consiste em um processo iterativo onde as variáveis são ajustadas de maneira simples, cumprindo os requerimentos, minimizando o consumo de potência e atingindo as especificações. Além disso, neste trabalho é incluída uma análise teórica dos requerimentos estáticos e dinâmicos, além de uma nova estratégia para a implementação do layout com a qual se obtém um baixo consumo de área. O DAC foi projeto e implementado em tecnologia CMOS de 0,35?m 4M2P. Alguns resultados obtidos no teste experimental são: área ativa do layout de 200?m×200?m, Corrente de escala completa de 700?A (uma tensão de alimentação de 3,3V), INL=0,3LSB, DNL=0,37LSB, SFDR=58dB para um sinal senoidal de saída de 1MHz e 50MHz de frequência de amostragem, SFDR=52dB para um sinal senoidal de saída de 1MHz e 10MHz de frequência de amostragem. / This work presents a digital-to-analog converter (DAC) design used in a RF transmitter stage for Bluetooth applications. A DAC is used in a RF transmitter because digitally processed signals must be transmitted as an analog wave to other radio stations. The DAC design must fulfill specifications of: sampling frequency, resolution, Spurious-Free Dynamic Range (SFDR), Signal-to-Noise Ratio (SNR) and Differential and Integral Nonlinearities (DNL, INL). These specifications are determined by the modulation standard of the RF transmission stage which in our work is Bluetooth. Also, low power and reduced area are required conditions to implement portable systems. Current-steering segmented architecture is suitable for this application [1]. It is based on an array of matched current sources that are switched to generate the output voltage. The Current sources design in a current steering DAC determines the converter\'s static and dynamic behavior. However, in the literature many works did not present a good design estrategy. As a solution, this work presents a study of the variables tradeoffs and a simple design strategy for current-steering segmented DAC design. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing.

Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction. At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145. Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC. Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave. HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.

abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB. The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

The work deals with design of the converter digital to analog on transistor level. Requirements converter a minimum resolution of 10 bits, short conversion time, low power and small chip area. For the realization of the converter is selected technology I3T25

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

This master’s thesis deals with design of two channel digital to analog converter for automotive applications. In first part, different topologies of D/A converters and their properties are discussed, with focus on current steering topology. Second part deals with design of convertor topology and current steering application. In third part, all parts of designed convertor are described and simulations results are presented. The designed two channel D/A converter has differential current output with 11b resolution per channel.