Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Photovoltaic (PV) systems are a rapidly growing segment in the renewable energy industry.  Though they have humble origins and an uncertain future, the commercial viability of PV has significantly increased, especially in the past decade.  In order to make PV useful, however, significant effort has to go into the power conditioning systems that take the low-voltage dc from the panel and create utility compatible ac output.  Popular architectures for this process include the centralized inverter and the distributed micro-inverter, each with its own advantages and disadvantages.  One attempt to retain the advantages of both architectures is to centralize the inverter function but construct PV panel-level micro-converters which optimize the panel output and condition the power for the inverter.  The main focus of this work is to explore the technical challenges that face the evolution of the dc-dc micro-converter and to use them as a template for a vertically integrated design procedure. The individual chapters focus on different levels of the process:  topology, modulation and control, transient mitigation, and steady-state optimization.  Chapter 2 introduces a new dc-dc topology, the Integrated Boost Resonant (IBR) converter, born out of the natural design requirements for the micro-converter, such as high CEC efficiency, simple structure, and inherent Galvanic isolation.  The circuit is a combination of a traditional PWM boost converter and a discontinuous conduction mode (DCM), series resonant circuit.  The DCM operation of the high-frequency transformer possesses much lower circulating energy when compared to the traditional CCM behavior.  When combined with  zero-current-switching (ZCS) for the output diode, it results in a circuit with a high weighted efficiency of 96.8%.  Chapter 3 improves upon that topology by adding an optimized modulation scheme to the control strategy.  This improves the power stage efficiency at nominal input and enhances the available operating range.  The new, hybrid-frequency method utilizes areas where the modulator operates in constant-on, constant-off, and fixed-frequency conditions depending on duty cycle, the resonant period length, and the desired input range.  The method extends the operating range as wide as 12-48V and improves the CEC efficiency to 97.2% in the 250-W prototype.  Chapter 4 considers the soft-start of the proposed system, which can have a very large capacitive load from the inverter.  A new capacitor-transient limited (CTL) soft-start method senses the ac transient across the resonant capacitor, prematurely ending the lower switch on-time in order to prevent an excessive current spike.  A prototype design is then applied to the IBR system, allowing safe system startup with a range of capacitive loads from 2μF to 500μF and a consistent peak current without the need for current sensing.  Chapter 5 further investigates the impact of voltage ripple on the PV output power.  A new method for analyzing the maximum power point tracking (MPPT) efficiency is proposed based on panel-derived models.  From the panel model, an expression demonstrating the MPPT efficiency is derived, along with a ripple "budget" for the harmonic sources.  These ripple sources are then analyzed and suggestions for controlling their contributions are proposed that enable circuit designers to make informed and cost-effective design decisions.  Chapter 6 illustrates how results from a previous iteration can provide a basis for the next generation's design.  A zero-voltage-switching (ZVS) version of the circuit in Chapter 2 is proposed, requiring only two additional MOSFETs and one inductor on the low-voltage side.  The maximum switching frequency is then increased from 70kHz to 170kHz, allowing for a 46% reduction in converter volume (from 430cm³ to 230cm³) while retaining greater than 97% weighted efficiency. / Ph. D.

The duty cycle control (DCC) modulation scheme for the three-phase dual-active-bridge (3p-DAB) DC-DC converter is a promising three degree-of-freedom modulation scheme which can extend the converter’s soft-switching range and reduce conduction losses under partial loading and wide voltage variations. However, the prior suggested methods to implement DCC in 3p-DABs have drawbacks such as requiring a multi-frequency approximation and offline optimization process or achieving less than optimal efficiency. To overcome these challenges, this research first proposes an optimal DCC modulation strategy (OMS) for the 3p-DAB based on a novel piece-wise time-domain analysis (TDA) and optimization process that obtains the optimal control parameters for minimum RMS phase current. Secondly, this research proposes a novel closed-form minimum current stress optimization (MCSO) DCC scheme based on the theoretical findings of the TDA optimization. The MCSO reduces the transformer phase currents and extends soft-switching operation under partial loading and wide voltage variations. Experimental results via open-loop testing show that the proposed closed-form MCSO DCC scheme has virtually identical efficiency as the OMS, making this the first research to provide a closed-form DCC modulation scheme for a 3p-DAB that achieves efficiency results equivalent to a fully-optimized offline scheme, but without the drawbacks of the offline optimization process. / Thesis / Master of Applied Science (MASc)

Electric vehicle (EV) adoption continues to rise, yet EV sales still represent a small portion of vehicle sales in most countries. An expansion of the DC fast charging (DCFC) network is likely to accelerate this revolution towards sustainable transportation, giving drivers more flexible options for charging on longer trips. However, DCFC presents a large load on the grid which can lead to costly grid reinforcements and high monthly operating costs – adding energy storage to the DCFC station can help mitigate these challenges. This thesis first performs a comprehensive review of DCFC stations with energy storage, including motivation, architectures, power electronic converters, and detailed simulation analysis for various charging scenarios. The review is closely tied to current state-of-the-art technologies and covers both academic research contributions and real energy storage projects in operation around the world. It is identified that the battery energy storage systems (BESSs) with active front end converter provides high efficiency with reasonable power density in a DCFC station. It is also realized that the isolated DC/DC converter interfacing BESS and EV determines the overall efficiency of a DCFC station with a low grid connection. Secondly, this thesis analyzes the impact of active front end based DCFC stations connected to a grid distorted with background voltage harmonics. In active front end based DCFC stations, background voltage harmonics produce current not only at the frequencies of the distorted voltage, but also at other coupled frequencies. Various mitigation techniques, such as increasing inner control loop gain, grid voltage feedforward, and selective harmonic compensation, have been adopted in industry to reduce the emissions originating from distorted background voltage. However, although these techniques are effective in suppressing the current at the harmonic orders present in the background voltage, they deteriorate the emission at coupled frequencies. This thesis provides the theoretical explanation of this phenomenon, which is verified by simulation of a two-level active front end in PSCAD/EMTDC. This thesis also discusses the proper treatment of current emission due to background voltage harmonics. Thirdly, the thesis identifies the semi dual active bridge (semi-DAB) converter as an ideal candidate as the interfacing isolated DC/DC converter between the BESS and the BEV. A novel control strategy is proposed for the semi-DAB converter to achieve wide voltage gain while increasing the efficiency at operational points with high input voltage and low output voltage, which is a commonly occurring scenario when the BESS is fully charged, and the EV battery is at low charge. Furthermore, this thesis also provides an algorithm to determine the required phase-shift in real time for any operating point, eliminating the need to devise the control trajectory offline. A 550 V, 10 kW experimental prototype is built and tested to validate the proposed control strategy. With a 25 A constant charging current, the prototype shows the proposed control strategy can improve efficiency by up to 3.5% compared to the well-known dual phase shift control at operating points with high input voltage (450 – 550 V) and low output voltage (150 – 275 V), with a peak efficiency of 97.6%. Finally, this thesis proposes a novel variable turns-ratio semi-DAB converter to improve its overall efficiency even further when the input voltage is high and the output voltage is low. Furthermore, a control law is also proposed to determine the turns-ratio, i.e., the operational structure of the converter, which reduces the converter peak and rms current. The 550 V, 10 kW prototype is modified to accommodate the variable turns-ratio high frequency transformer to test the proposed converter and control. The proposed converter with control can further improve the efficiency at many operating points compared to single turns-ratio semi-DAB with DPS control. The peak efficiency achieved is 98.5%. / Thesis / Doctor of Philosophy (PhD)

Current trends in electronics are toward the use of reduced voltages. In the past, 5 V and higher voltages have been the standard, however, currently, 3.3V and 2.5V circuits are becoming increasingly common. While the operating voltage is decreasing, electronic systems are becoming more complex. The net result is that in many, cases, the current required by the next generation of electronics will be far greater than in the past. These increased currents and low voltages pose dramatic problems for designers not the least of which is the effect of electronic packaging and circuit implementation on the overall power supply performance. In addition, for many applications, space and weight are at a premium and converters are needed to power low voltage circuit assemblies that are highly efficient, low in weight, and small in total height and foot print. This dissertation addresses these trends and needs through the design, fabrication and evaluation of a 3.3V DC/DC converter. Designs of 3.3V, 2.5V, and 1.5V are presented and evaluated while a 3.3V, 100 watt converter with a power density of 157 watts/in³ has been fabricated and evaluated in a miniature form. This converter utilizes a implementation strategy developed by the author which was selected due to its ability to handle the current levels required and its compact size. Specific contributions of this work include: • Analysis of the effects of packaging on low voltage high current converters in order to provide a guideline for converter implementation. This analysis has been performed for 3.3 V, 2.5 V, and 1.5 V designs, respectively. • Development of high efficiency 2.5 V, 100 watt and 1.5 V, 75 watt designs based on previously reported half bridge topologies. • Development of a packaging strategy which allows the fabrication of low voltage compact converters with high efficiency. A 3.3 V converter has been fabricated and with the simulated data validated these experimental results. For very low (less than 50 watts and / or less than 10 amps) and high power levels (hundreds of amps or kilowatts), the implementation strategy is normally clear; PCB/IMS, and DBC respectively. However, for applications in the middle range of power or current level, the optimum implementation is often unclear. The question that this work seeks to answer is under what conditions are different implementation schemes most suitable. / Ph. D.

The demand for high power density, high efficiency bus converters has increased interest in resonant topologies, particularly the LLC resonant converter. LLC resonant converters offer several advantages in efficiency, power density, and hold up time extension capability. Among high voltage (>500V) MOSFETs, Super Junction MOSFETs, such as Infineon's CoolMOS parts, offer lower Rds on than conventional parts and are a natural choice for this application to improve efficiency. However, there is a history of converter failure due to reverse recovery problems with the primary switch's body diode. Before selecting CoolMOS devices for use in a LLC resonant converter, it is necessary to investigate its performance in this application. Field failures of PWM soft switching phase shift full bridge converters have been attributed to large reverse recovery charge in the primary side MOSFET body diode. Under low load conditions the device cannot fully recover, and the large reverse recovery current can cause the device to enter secondary break down, leading to failure. The unique structure of Super Junction MOSFETs, such as CoolMOS, avoid this failure mode by providing a different path for the reverse current; however, the reverse recovery charge of CoolMOS devices is large and can cause a loss of efficiency. For this reason, it is important to avoid conditions under which the reverse recovery characteristics of the body diode can be seen. / Master of Science

L'avion plus électrique est un concept qui a le vent en poupe chez les principaux constructeurs du domaine de l'aéronautique. Dans ce domaine, comme dans d'autres, les besoins en énergie électrique sont croissants et nécessitent de mettre en place des systèmes de conversion d'énergie fiables, performants et modulaires. Ces systèmes de conversion sont souvent couplés avec des systèmes de stockage d'énergie (type batterie) permettant dans certaines situations de rendre l'avion énergétiquement autonome grâce à une source de puissance indépendante des principaux organes de production d'énergie. Cette interconnexion batterie - réseau de bord présente un rapport de tension élevé ce qui, ajouté aux fortes valeurs de courant de la basse tension, en fait un objet particulièrement complexe à réaliser.L'objectif de cette thèse est de concevoir de manière optimale un convertisseur de puissance isolé permettant l'interconnexion d'un bus basse tension 28 V (typiquement des batteries) à un bus haute tension 540 V (réseau de bord de l'avion) avec une puissance échangeable d'environ 12 kW. Elle se déroule dans le cadre d'un projet ANR (quatre partenaires universitaires, associés à l'entreprise AIRBUS) dont l'une des tâches est le développement d'outils de conception pour l'électronique de puissance. Le travail correspondant comprend une contribution à cette tâche sous forme de la construction de modèles des principaux composants intervenant dans un convertisseur, modèles destinés à être intégrés dans les routines d'optimisation. Pour cette raison, ils seront analytiques (physique, empiriques, mélange des deux).Ces modèles seront ensuite insérés dans un outil global développé dans une autre thèse du projet, à l'aide duquel différentes architectures de convertisseurs seront comparées afin d'en déduire la meilleure solution pour le cahier des charges énoncé précédemment. Un prototype du convertisseur retenu sera finalement réalisé en utilisant des technologies avancées, pour conduire une validation expérimentale. / The electric aircraft tends to become widespread at all the main manufacturers of the domain of the aeronautics. Needs do not stop growing and require setting up reliable, efficiency and modular systems of conversion of energy. These systems of conversion are often coupled with systems of storage of energy (battery) allowing in certain situations to make the punctually autonomous aircraft energetically thanks to a source of power independent from main organs of power production. This interconnection battery - network of edge presents a very high report of rise of tension what, added to the high current value of the battery bus, in fact a particularly complex object to be realized.The objective of this thesis is to design in an optimal way a converter of power isolated allowing the interconnection of a low-voltage bus 28V (typically batteries) in a high-voltage bus 540V (network of edge of the aircraft) with an exchangeable power about 12 kW. It takes place within the framework of an ANR project (four university partners + AIRBUS) the development of tools of conception of which one of the tasks is for the ENP. The corresponding work includes a contribution to this task in the form of the construction of models of the main components occurring in a converter, model intended to be integrated into the routines of optimization. For that reason, they will be analytical (physical, empirical or mix both).These models will then be inserted into a global tool developed in another thesis of the project, by means of which various architectures of converters will be compared to deduct the best solution from it for the previous specifications. A prototype of the reserved converter will be finally realized by using advanced technologies, to lead an experimental validation.

Master’s thesis deals with the design concept of DC/DC convertor usable for a backup source with supercapacitors. The paper describes the theoretical knowledge of supercapacitors technology, principle of basic DC/DC convertors and their use in electrical energy storage systems. The thesis contains a description of the designed backup power system and its properties, which has been measured.

This diploma thesis deals with design and subsequent realization of DC / DC converter for supply of matrix LED fields for the automotive industry. Such a converter must be able to supply a current of several Amperes and a voltage of the order of tens of Volts. Matrix headlights are currently being developed by a number of automotive companies. These headlamps allow independently to control the intensity of light incident on different objects or people who are in front of a car. In addition to the front headlamps the matrix LED lights are also used in the rear and signaling lights. Here it serves mainly to create different animations that have no function except the overall enhancement appearance of the vehicle. All of these lights need power units that will be suitable to regulate current flowing into various combinations of LEDs illuminated.