In recent years, there has been lots of emphasis put on the development of renewable energy. While considerable improvement on renewable energy has been made, there are some inherent limitations for these renewable energies. For example, for solar and wind power, there is an intermittent nature. For the fuel cell, the dynamics of electro-chemical reaction is quite slow compared to the electric load. This will not be acceptable for modern electric application, which requires constant voltage of constant frequency. This work proposed and evaluated a new power circuit that can deal with the problem of the intermittent nature and slow response of the renewable energy. The proposed circuit integrates different renewable energy sources as well as energy storage. By integrating renewable energy sources with statistical tendency to compensate each other, the effect of the intermittent nature can be greatly reduced. This integration will increase the reliability and utilization of the overall system. Moreover, the integration of energy storage solves the problem of the slow response of renewable energy. It can provide the extra energy required by load or absorb the excessive energy provided by the energy sources, greatly improving the dynamics of overall system. To better understand the proposed circuit, "Dual Active Bridge" and "Triple Active Bridge" were reviewed first. The operation principles and the modeling were presented. Analysis and design of the overall system were discussed. Controller design and stability issues were investigated. Furthermore, the function of the central controller was explained. In the end, different simulations were made and discussed. Results from the simulations showed that the proposed multi-port DC-DC power converter had satisfactory performance under different scenarios encountered in practical renewable energy application. The proposed circuit is an effective solution to the problem due to the intermittent nature and slow response of the renewable energy.

Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened. The second topic is focused on the implementation of an analog front-end of digital cordless headset baseband controller. The integrated analog and digital interface IC provides an interface for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which will be processed by the baseband controller. It also converts an 8-bit digital voice data into an analog voice signal. In addition, a built-in oscillator is included in the design, which provides a global clock signal. The third topic is to carry out an DC/DC converter with a built-in voltage detector. The converter can convert 1.5V input voltage to 2.7V output voltage. A portable system can use only one single battery to power on by this circuit. It also contains a voltage detector to indicate whether the output voltage meets the pre-determined level.

In this thesis analysis and design of a wide input range DC-DC converter is proposed along with a robust power control scheme. The proposed converter and its control is designed to be compatible to a fuel cell power source, which exhibits 2:1 voltage variation as well as a slow transient response. The proposed approach consists of two stages: a primary three-level boost converter stage cascaded with a high frequency, isolated boost converter topology, which provides a higher voltage gain and isolation from the input source. The function of the first boost converter stage is to maintain a constant voltage at the input of the cascaded DC-DC converter to ensure optimal performance characteristics with high efficiency. At the output of the first boost converter a battery or ultracapacitor energy storage is connected to take care of the fuel cell slow transient response (200 watts/min). The robust features of the proposed control system ensure a constant output DC voltage for a variety of load fluctuations, thus limiting the power being delivered by the fuel cell during a load transient. Moreover, the proposed configuration simplifies the power control management and can interact with the fuel cell controller. The simulation results and the experimental results confirm the feasibility of the proposed system.

This thesis comprises two topics : the first one is the design and implementation of FlexRay automotive communication system physical layer. The second part is the design of a high efficiency DC/DC Buck converter with sub-3 ¡Ñ VDD. The first topic discloses the physical layer design comprising the Bus Guardian and the Bus Driver used in an in-vehicle network compliant with FlexRay standards. It is realized in a mixed-signal chip using TSMC 1P6M 0.18 £gm CMOS process. Its core area is less than 0.8 mm2, and power consumption is less than 60 mW. The second topic is to design a DC to DC step-down converter, which can accommodate wide range VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the design is realized by a typical 1P6M 0.18 £gm CMOS process without any high voltage technology. The core area is less than 0.184 mm2, while the VDD range is up to 5 V. Since the internal reference voltage is 1 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of power supply. Therefore, it can be integrated in a system chip to provide multiple supply voltage sources.

This thesis is an ongoing project of Ericsson with collaboration of Blekinge Institute of Technology [BTH], and Linneaus University [LNU] to compare the functionality and performance of three controllers Polynomial Pole Placement, PID [Proportional Integral Derivative] and PD controller in third order. This paper presents the state space modeling approach of DC-DC Buck converter. The main aim of this thesis is, by considering the buck converter system of Ericsson BMR450 with the PID, POLYNOMIAL and PD controllers at feedback loop, thus running their Matlab file with their appropiate Simulink block diagram, and comparing the three controllers performance by verifying their appropiate output graphs. The third order controller design is complicated and response is slow. The second order design is easy and gives better responses than third order Polynomial, PID and PD controllers. / As per the results point of view, the polynomial performed well than PID and PD controllers. The simulations show that the polynomial controller reaches the reference voltage very well, were the PID and PD result does not differ very much while meeting with the required reference voltage. Thus we conclude that the Polynomial controller design and results were better than the PID and PD Controllers. If we compare both the second order [4] and third order controller methods, The second order controllers are easy in design and gives better responses than third order polynomial PID and PD controllers. / ERCS.MADHU KIRAN, D.NO: 1/1/131, B.C.COLONY, MUTHUKUR, NELLORE, ANDHRA PRADESH, INDIA. PIN - 524344. THOTA. Partha Saradhi, C/O CH SUVARNA RAJU D.NO: 4-5-47, VEGIVARI CHAVADI, KOTHA PETA, WARD NO:21, KOVVUR, WEST GODAVARI,ANDHRA PRADESH, INDIA PIN - 534350,

This thesis presents the design of a step-up DC-DC converter with on-chip coupled inductors. Circuit theory of DC-DC converters in general is presented, after which a mathematical model of a step up converter is developed. A circuit implementation optimized from results of the mathematical model follows. For a completely integrated step-up converter, the inductor size is reduced by increasing the frequency of operation and using a circuit topology that employs coupled inductors. Spiral inductors are also studied to achieve maximum quality factor and inductance. A fast PWM control system is used to regulate the high-frequency converter. The fabrication was done in standard TSMC 0.18-$\mu$m digital CMOS process for four circuits, including one with a conventional topology and the others with a coupled inductor topology with varying inductor geometries. Measurement results from a fabricated prototype have been presented, demonstrating the functionality of the four circuits with coupled inductors on the fabricated chip and the improvement of the coupled solution over the conventional design. It is demonstrated that the circuits with coupled inductors have a significant improvement in performance based on conversion ratio and efficiency. Finally, the design process is evaluated and recommendations are made for future work. Furthermore, a new self-oscillating and robust control system is proposed that enables simpler and more efficient regulation for high-frequency converters such as one developed for this thesis.

As the speed and power demands on Buck converters continue to increase, it has become time to replace the linearly-controlled conventional Buck converter. Digital circuits, such as microprocessors, are requiring higher dynamic currents, at lower voltages, than ever before. Traditionally, such Buck converters have been controlled by linear voltage-mode or current-mode control methods. While these controllers offer such advantages as fixed switching frequencies and zero steady-state error, their reaction speed is inherently limited by their bandwidth which is a fraction of the converter switching frequency. Therefore, to improve the transient response of a Buck converter in a practical manner, four novel ideas are presented in this thesis. The first contribution is an analog “charge balance controller”. The control method utilizes the concept of capacitor charge balance to achieve a near-optimal transient response for Buck converters undergoing a rapid load change. Unlike previous work, the proposed controller does not require expensive and/or slow analog multipliers/dividers. In addition, the nominal inductance value is not required by the proposed controller. Simulation and experimental results demonstrate a significant improvement in transient performance over that of a linear voltage-mode controller. For low duty cycle applications, the unloading transient performance of a Buck converter tends to be poor when compared to the corresponding loading transient performance. Therefore, the second contribution is an auxiliary circuit and an analog auxiliary controller which drastically improves the performance of a Buck converter undergoing an unloading transient. Significant overshoot reduction was observed over that of a linearly-controlled conventional Buck converter. The third contribution is a digital implementation of the aforementioned “charge balance control” concept. Through digital implementation the control law is extended to include load-line regulation. Unlike previous work, large lookup tables are not required to perform complex mathematical functions, thus the number of required gates is significantly reduced. The final contribution is a digital implementation of the “charge balance controller” capable of operating with the previously-mentioned auxiliary circuit. This complete solution is capable of improving the voltage deviation caused by loading and unloading transients. In addition, the combined auxiliary circuit and control law is extended to load-line regulation applications. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2010-01-31 23:01:24.606

Improved transient performance and converter miniaturization are the major driving factors behind high frequency operation of switching power supplies. However, high speed operation is limited by topology, control, semiconductor, and packaging technologies. The inherent mitigation of switching loss in resonant converters makes them prime candidates for use when the limits of switching frequency are pushed. The goal of this thesis is to address two areas that practically limit the achievable switching frequency of resonant topologies. Traditional control methods based on single cycle response are impractical at high frequency; forcing the use of pulse density modulation (PDM) techniques. However, existing pulse density modulation strategies for resonant converters in dc/dc applications suffer from: • High semiconductor current stress. • Slow response and large filter size determined by the low modulating frequency. • Possibly operating at fractions of resonant cycles leading to switching loss; thereby limiting the modulating frequency. A series resonant converter with variable frequency PDM (VF-PDM) with integral resonant cycle control is presented to overcome the limitations of existing PDM techniques to enable efficient operation with high switching frequency and modulating frequency. The operation of the circuit is presented and analyzed, with a design procedure given to achieve fast transient performance, small filter size, and high efficiency across the load range with current stress comparable to conventional control techniques. It is shown that digital implementation of the controller can achieve favourable results with a clock frequency four times greater than the switching frequency. Driving the synchronous rectifiers is a considerable challenge in high current applications operating at high switching frequency. Resonant gate drivers with continuous inductor current experience excessive conduction loss, while discontinuous current drivers are subject to slow transitions and high peak current. Current source drivers suffer from high component count and increased conduction loss when applied to complementary switches. A dual-channel current source driver is presented as a means of driving two complementary switches. A single coupled inductor with discontinuous current facilitates low conduction loss by transferring charge between the MOSFET gates to reduce the number of semiconductors in the current path, and reducing the number of conduction intervals. The operation of the circuit is analyzed, and a design procedure based on minimization of the total synchronous rectifier loss is presented. Implementation of the digital logic to control the driver is discussed. Experimental results at megahertz operating frequencies are presented for both areas addressed to verify the theoretical results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2012-09-09 20:43:56.997

The proposed research objective is to develop, test, and evaluate a mixer and charger-supply CMOS IC that derives and mixes energy and power from mixed sources to accurately supply a miniaturized system. Since the energy-dense source stores more energy than the power-dense source while the latter supplies more power than the former, the proposed research aims to develop an IC that automatically selects how much and from which source to draw power to maximize lifetime per unit volume. Today, the state of the art lacks the intelligence and capability to select the most appropriate source from which to extract power to supply the time-varying needs of a small system. As such, the underlying objective and benefit of this research is to reduce the size of a complete electronic system so that wireless sensors and biomedical implants, for example, as a whole, perform well, operate for extended periods, and integrate into tiny spaces.

Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.