Made available in DSpace on 2016-04-04T18:31:26Z (GMT). No. of bitstreams: 1 Adenilson Boccato de Almeida.pdf: 2733171 bytes, checksum: 5b2d37bdad4b16ff26ccb172bbd6fbfc (MD5) Previous issue date: 2008-12-18 / This dissertation examines the quality of the transmission of VoIP (Voice over IP) in wireless LAN (Local Area Network Wireless). To achieve this objective tests were performed on the bench using voice codecs G729, G711, G723 and GSM analyzing characteristics of delay and loss of packets. The paper presents results that indicate the effect of the phenomena of instability of wireless networks in the performance of VoIP. These variations show significant changes in the quality of voice depending on the used environment and the distance between the transmitter and receiver. / Esta disserta??o analisa a qualidade da transmiss?o do VoIP (Voz sobre IP) em rede WLAN (Wireless Local ?rea Network). Para atingir esse objetivo foram realizados testes em bancada utilizando os codecs de voz G729, G711, G723 e GSM analisando suas caracter?sticas de atraso e perda de pacotes. O trabalho apresenta resultados que indicam o efeito dos fen?menos de instabilidade das redes sem fio no desempenho do VoIP. Essas varia??es revelam altera??es significativas na qualidade da voz em fun??o do ambiente utilizado e da dist?ncia entre o emissor e receptor.

<p>This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.</p><p>The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).</p><p>The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.</p><p>A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.</p><p>When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.</p><p>The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.</p>

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF). The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project. A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa. When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s. The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

The reliability and data rate of wireless communication have traditionally been limited by the presence of multipath fading in wireless channels. However, dramatic performance improvements can be obtained by the use of multiple transmit and receive antennas. Specifically, multiple antennas increase reliability by providing diversity gain, namely greater immunity to deep channel fades. They also increase data rates by providing multiplexing gain, i.e., the ability to multiplex multiple symbols in one signaling interval. Harvesting the potential benefits of multiple antennas requires the use of specially designed space-time codes at the transmitter front-end. Space-time codes introduce redundancy in the transmitted signal across two dimensions, namely multiple transmit antennas and multiple signaling intervals. In this work, we focus on linear space-time codes, which linearly combine the real and imaginary parts of their complex inputs to obtain transmit vectors for multiple signaling intervals. We aim to design optimum linear space-time codes. Optimality metrics and design principles for space-time codes are shown to depend strongly on the codes' function in the overall transmitter architecture. We consider two cases, depending on whether or not the space-time code is complemented by a powerful outer error-control code. In the absence of an outer code, the multiplexing gain of a space-time code is measured by its rate, while its diversity gain is measured by its raw diversity order. To maximize multiplexing and diversity gains, the space-time code must have maximum possible rate and raw diversity order. We show that there is an infinite set of maximum-rate codes, almost all of which also have maximum raw diversity order. However, different codes in this set have different error rate for a given input alphabet and SNR. Therefore, we develop analytical and numerical optimization techniques to find the code in this set which has the minimum union bound on error rate. Simulation results indicate that optimized codes yield significantly lower error rates than unoptimized codes, at the same data rate and SNR. In a concatenated architecture, a powerful outer code introduces redundancy in the space-time code inputs, obtaining additional diversity. Thus, the raw diversity order of the space-time inner code is only a lower limit to the total diversity order of the concatenated transmitter. On the other hand, we show that the rate of the space-time code places an upper limit on the multiplexing ability of the concatenated architecture. We conclude that space-time inner codes should have maximum possible rate but need not have high raw diversity order. In particular, the serial-to-parallel converter, which introduces no redundancy at all, is a near-optimum space-time inner code. This claim is supported by simulation results. On the receiver side, we generalize the well known sphere decoder to develop new detection algorithms for stand-alone space-time codes. These new algorithms are extended to obtain efficient soft-output decoding algorithms for space-time inner codes.

The conception of turbo codes by Berrou et al. has created a renewed interest in modern graph-based codes. Several encouraging results that have come to light since then have fortified the role these codes shall play as potential solutions for present and future communication problems. This work focuses on both practical and theoretical aspects of graph-based codes. The thesis can be broadly categorized into three parts. The first part of the thesis focuses on the design of practical graph-based codes of short lengths. While both low-density parity-check codes and rateless codes have been shown to be asymptotically optimal under the message-passing (MP) decoder, the performance of short-length codes from these families under MP decoding is starkly sub-optimal. This work first addresses the structural characterization of stopping sets to understand this sub-optimality. Using this characterization, a novel improved decoder that offers several orders of magnitude improvement in bit-error rates is introduced. Next, a novel scheme for the design of a good rate-compatible family of punctured codes is proposed. The second part of the thesis aims at establishing these codes as a good tool to develop reliable, energy-efficient and low-latency data dissemination schemes in networks. The problems of broadcasting in wireless multihop networks and that of unicast in delay-tolerant networks are investigated. In both cases, rateless coding is seen to offer an elegant means of achieving the goals of the chosen communication protocols. It was noticed that the ratelessness and the randomness in encoding process make this scheme specifically suited to such network applications. The final part of the thesis investigates an application of a specific class of codes called network codes to finite-buffer wired networks. This part of the work aims at establishing a framework for the theoretical study and understanding of finite-buffer networks. The proposed Markov chain-based method extends existing results to develop an iterative Markov chain-based technique for general acyclic wired networks. The framework not only estimates the capacity of such networks, but also provides a means to monitor network traffic and packet drop rates on various links of the network.

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Cette thèse traite des systèmes MIMO à multiplexage spatial, associés à la modulation OFDM. L'étude s'attarde particulièrement sur les systèmes 4x4, inclus ou à l'étude dans les normes 3GPP LTE et 3GPP LTE-A. Ces dimensions particulières nécessitent une étude de conception poussée du récepteur. Il s'agit notamment de proposer des détecteurs qui affichent à la fois de bonnes performances, une faible latence et une complexité de calcul réalisable dans un système embarqué. Le défi consiste plus particulièrement à proposer un détecteur offrant des performances quasi-optimales, tout en ne nécessitant qu'une complexité de calcul polynomiale. Une attention particulière est prêtée aux problèmes d'implantation. Ainsi, avantage est donné aux algorithmes à complexité fixe et permettant la réalisation d'opérations en parallèle. En réponse aux problématiques rencontrées, l'architecture du détecteur requiert une attention particulière. Le choix stratégique adopté est de chercher à transférer au prétraitement - qui ne dépend pas des données - le plus possible de complexité de calcul. Au cours de ce travail et suite à l'introduction du contexte général et des principaux pré-requis, l'inventaire des grandes tendances dans la littérature en ce qui concerne les détecteurs à décision dure est fait. Ils constituent le coeur du sujet et un détecteur original est proposé, incluant notamment les aspects de réduction de réseau et de décodage sphérique. Son avantage par rapport aux techniques existantes est ainsi démontré, et les résultats prometteurs sont maintenus lors de son extension à la décision souple. Comme attendu, le choix de transférer au prétraitement la complexité de calcul s'avère gagnant. Notamment, la réduction de complexité de calcul qu'il permet est présentée dans cette thèse. Parmi les principaux résultats, ce travail a débouché sur la proposition d'un détecteur original, qui a démontré un compromis entre performance et complexité de calcul efficace. Notamment, il requiert une complexité de calcul presque constante - selon les tailles de constellation -, tout en offrant des performances proches du maximum de vraisemblance. Par conséquent, le détecteur à décision souple proposé se positionne par rapport à l'état de l'art comme une solution d'une grande efficacité dans les systèmes 4x4.

Les communications mobiles sans fil ont connu un progrès très rapide pendant les dernières décennies. Ca a commencé avec les services vocaux offerts par les systèmes de la première génération en 1980, arrivant jusqu'aux systèmes de la quatrième génération avec des services internet haut débit et un nombre important d'utilisateurs, et dans quelques années les systèmes de la cinquième génération avec encore plus de débit et d'utilisateurs. En effet, les caractéristiques essentielles qui définissent les services et les qualités des services dans les systèmes de communication sans fil sont: le débit, la fiabilité de transmission et le nombre d'utilisateurs. Ces caractéristiques sont fortement dépendantes et liées entre elles, et sont soumises à la gestion des interférences entre les différents utilisateurs. Les interférences entre-utilisateurs arrivent quand plusieurs émetteurs, dans une même zone, envoient simultanément à leurs propres destinataires en partageant la même bande de fréquence. Dans cette thèse, nous nous intéressons à la gestion d'interférence entre utilisateurs, méthodes classiques et avancées, de deux côtés émission et réception. Ensuite, nous proposons des nouvelles contributions dans des différents contextes afin d'améliorer les performances. Cette thèse est divisée en plusieurs parties. Dans la première partie, une présentation concise de l'état de l'art sur des techniques de gestion et de réduction d'interférences entre utilisateurs. Ensuite, nous introduisons le concept d'une méthode dite d'Alignement d'Interférence, où nous proposons des améliorations algorithmiques dans les canaux mono-antenne afin d'augmenter le débit. Enfin, nous supposons les deux cas suivants: l'application et l'absence du schéma d'IA à l'émission, et nous proposons d'utiliser des méthodes existantes ou bien nouvelles pour la détection du côté récepteur.