Kvaliteten på produkterna som tillverkas av SME företag har hög betydelse för deras konkurrenskraft. Att kunna producera skräddarsydda artiklar med hög kvalitet samt kunna leverera i tid och enligt specifikation är några av de vanligaste krav stora företag ställer som kunder. Tillverkande SME företag differentierar sig gentemot konkurrenter genom att digitalisera sina processer. Behovet av digitala verktyg kan dock också anses vara en överlevandsfaktor ty kundernas krav blir allt högre desto mer automatiserade kundernas fabriker blir. Att övergå till en digitaliserad kvalitetsäkringsprocess för SME:er är inte enkelt. En del av problematiken kopplad till övergången mot en digitaliserad kvalitetssäkringsprocess är saknaden av IT kunskap och de begränsade medlen som SME bolag har. Syftet med arbetet är att analysera användandet av digitala mätverktyg som kan användas i kvalitetssäkringsprocessen hos tillverkande SME företag samt analysera hur denna implementation kan utföras på bästa möjliga sätt. För att nå detta syfte svarade arbetet på följande frågeställningar: 1) Vilka processer för kvalitetssäkring använder tillverkande SME företag i dagsläget? 2) Hur kan digitala verktyg implementeras för att assistera kvalitetsäkringsprocessen hos tillverkande SME företag? 3) Vilka utmaningar finns det vid implementation av digitala stödverktyg för kvalitetssäkring i tillverkande SME företag? Arbetet är baserat på teorier om olika kvalitetssäkringsprocesser. Exempel på dessa är Lean, TQM och Six Sigma. Metoden som användes var en fallstudie på företaget Marcus Komponenter AB i Järna utanför Södertälje. I fallstudien användes det digitala mätsystemet MeasurLink som tillhandahålls av Mitotoyo, för att digitalisera kvalitetssäkringsprocessen av de tillverkade produkterna. Datainsamlingen i arbetet har utförts med hjälp av tre olika kvalitativa datainsamlingsmetoder; dokumentinsamlingsmetodik, intervjuer och observationer. Resultatet av arbetet visar på att företaget bör följa en handlingsplan så att de kan förbereda sig för att kunna implementera ett digitalt mätsystem fullskaligt i hela produktionen. Resultatet är viktigt ty det visar på att företag bör ha uppnått en viss mognadsgrad för att kunna implementera digitala mätsystem. Sammanfattningsvis har slutsatsen dragits att en storskalig implementation av MeasurLink vid närvarande inte är möjlig. Däremot kan implementationen utföras i mindre skala vid en teststation. När företaget byggt upp ett standardiserat arbetssätt kring mätning och dataanalys med hjälp av MeasurLink kan en fullskalig implementation genomföras. / The quality of products manufactured by SME companies is of high importance for their competitiveness. Being able to produce tailor-made items of high quality and being able to deliver on time and according to specification are some of the most common requirements large companies place as customers. Manufacturing SME companies differentiate themselves from competitors by digitalizing their processes. However, the need for digital tools can also be considered as a survival factor, as the demands of customers become higher the more automated customers' factories become. Switching to a digitalized quality assurance process for SMEs is not easy. Part of the problems associated with the transition to a digitalized quality assurance process is the lack of IT knowledge and the limited resources that SME companies have. The purpose of this bachelor’s thesis is to analyze the use of digital measuring tools that can be used in the quality assurance process in manufacturing SME companies. As well as to analyze how this implementation can be carried out in the best possible way. To achieve this goal, this thesis answered the following research questions: 1) What quality assurance processes do SME manufacturing companies currently use? 2) How can digital tools be implemented to assist the quality assurance process of manufacturing SMEs? 3) What are the challenges in implementing digital quality assurance tools in manufacturing SMEs? The thesis is based on theories of different quality assurance processes. Examples of these are Lean, TQM and Six Sigma. The method used was a case study at the company Marcus Komponenter AB in Järna outside Södertälje. In the case study, the digital measurement system MeasurLink provided by Mitotoyo was used to digitalize the quality assurance process of the manufactured products. The data collection has been carried out using three different qualitative data collection methods; document collection, interviews and observations. The result of the thesis shows that the company should follow an action plan so that they can prepare in order to be able to implement a digital measurement system full-scale throughout the production. The result is important because it shows that companies should have achieved a certain degree of maturity in order to be able to implement digital measurement systems. In summary, the conclusion of the case study was that a large-scale implementation of MeasurLink is currently not possible. However, the implementation can be done in a smaller scale, at a test station. Once the company has built up a standardized method of measurement and data analysis using MeasurLink, a full-scale implementation can be performed.

The COVID-19 pandemic impacted many around the world, some more than others, having socioeconomic impacts around the globe. Due to its rapid spread many countries implemented restrictions, such as quarantines to uphold social distancing between its citizens. In addition, the coronavirus has not only affected people’s way of life but also many companies’ financial health worldwide. This pandemic’s side effects has resulted in increased digital transformation, causing many companies without the required infrastructure to rapidly implement mechanism and strategies to handle this type of work style. This studies aim is to give an insight in employee’s experiences and reactions to a rapid digital implementation, in a company without the infrastructure in place. With the help of an inductive approach and a multi level framework, four themes emerged from the interviews conducted ImplementationConsequences, Organizational Support, Expectations of Digital Implementation and Work-related Differences. The results showed that there is a discrepancy between the necessary factors for a successful implementation, highlighted in the model used and the respondent’s answers. Linked to this was the gender differences, a new factor arising from the data collected, emphasising the difficulties linked to teleworking but affecting a proactive use of digital tools, and hence lowering the work productivity. Even though there were differences, there were also parables showing that acceptance, attitude, and involvement in the implementation, among other factors are crucial for an openness towards digitalization. Finally, these factors and their relationship with digital implementation as well as the pandemic were explored trough a multi level framework.

Three new and efficient carrier frequency offset estimators are created for the case of disjoint pilot symbol blocks. The estimators are efficient in both a statistical sense and a computational sense. They are formulated to reduce computational cost for use in real-time applications, such as FPGA (field programmable gate array) devices. A reduced cost maximum likelihood (ML) frequency estimator is described. It is a generalization of the approximate ML estimator for a single block of pilot symbols. A number of recent ML estimation techniques are integrated with the purpose of reducing the computational cost while preserving estimation performance. The estimator incorporates multirate signal processing methods, FFT periodogram searches, and directed periodogram searches. The subsequent relationships between FFT lengths, resampling rates, and search iterations is established. The proposed estimator exhibits very good accuracy, operating range, and a low SNR threshold, and has low cost. A data-aided frequency estimator based on the measurement of phase increments, is also derived. It has extremely low cost, but a high SNR threshold. However, its formulation is such that a careful analysis of the range error problem may be performed. From this analysis certain conclusions are made about proper pilot symbol organization, and these conclusions are applicable to other frequency estimators. The third estimator is a generalization of the autocorrelation frequency estimation technique. The generalizations are needed to account for the spacings between the pilot blocks. A novel iterative approach, incorporating a Kalman filter, is used to improve operating range. It is shown that the autocorrelation frequency estimator exhibits good accuracy while maintaining a useful operating range. Real-time architectures are described for the ML and autocorrelation frequency estimators using disjoint pilot blocks. The computational cost and estimation performance of the proposed estimators are analyzed and it is shown that they give estimation performance near to theoretical limits, while preserving wide operating range. We see that the autocorrelation estimator is appropriate for small numbers of pilot symbols, while the ML estimator is appropriate for large numbers of pilot symbols. The new frequency estimators are the first to be derived (for the case of disjoint blocks of pilot symbols) such that computational cost is kept low, while still achieving high accuracy, a wide operating range, and low SNR thresholds.

Digital interventions in healthcare have the potential to act as a positive approach to the demographical and social dilemmas existing in sparsely populated regions. Much emphasis lies on designing implementations that are beneficial and used to a large extent. The impact of responsible stakeholders in designing and implementing those interventions is vital to successful outcomes, but research about their perspective on the topic is lacking. The role of voluntariness in eHealth is unclear, and management’s view on determining factors that impact user adoption can contribute to the Information Systems literature. This study aimed to investigate healthcare management’s perspective regarding eHealth. A qualitative study was performed by conducting semi-structured interviews with management and decision-makers in Swedish healthcare on the regional and municipal levels. Their attitude towards the digitalization of healthcare is generally positive, and its benefits for the future are evident. Digitalizing the health sector is seen as necessary as long as equal care and high quality in healthcare can be maintained. Much work lies in increasing adherence to use eHealth solutions, and there is a desire to improve national coordination. Factors that influence adoption are generally compatible with existing technology acceptance literature, but the impact of some determinants differs. The results indicate that social influence has a more important impact in the voluntary context of eHealth than previous literature suggests. An introduction of mandatory elements in healthcare may have benefits for continuous use. Future research about the differences between voluntary and mandated contexts can give rich insight into how to view factors that affect technology adoption and adherence to eHealth solutions.

<p>This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.</p><p>The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).</p><p>The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.</p><p>A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.</p><p>When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.</p><p>The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.</p>

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF). The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project. A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa. When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s. The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

Les structures de conversion multi-niveaux parallèles permettent de faire transiter de fortscourants tout en gardant une bonne puissance massique ; celles-ci sont réalisées en parallélisantdes cellules de commutation. Cette parallélisation permet de réduire le courant dans chaquecellule et ainsi de revenir dans des gammes plus standard de composants de puissance. Laparallélisation, en utilisant une commande adaptée, améliore les formes d’onde en sortie duconvertisseur. Ce manuscrit se focalisera sur une structure de conversion multiniveaux parallèlespécifique constituée de bras de hacheur dévolteur en parallèles couplés magnétiquement. Eneffet du fait de la commande entrelacée mise en place, l’ondulation du courant de sortie se voitréduite mais en contrepartie l’utilisation d’inductances séparées sur chaque bras entraine uneaugmentation de l’ondulation des courants de bras, directement liée au nombre de cellules decommutation, en fonction de l’ondulation du courant de sortie. Afin de palier à ce problème cesinductances sont remplacées par un (ou plusieurs) coupleur(s) magnétique(s) qui permet(tent) deréduire l’ondulation de courant dans chaque bras. Cependant dans le but de garantir la nonsaturation ainsi qu’une bonne intégration des coupleurs il est nécessaire de s’assurer del’équilibrage des courants de chaque bras malgré une différence entre les paramètres. Ainsi cemanuscrit s’est axé vers la détermination de différentes méthodes de modélisation découplant lesystème permettant le maintien de l’égale répartition des courants en utilisant des différences derapports cycliques. Ces méthodes de modélisation ont été généralisées afin de réaliser unalgorithme permettant de générer des lois de commande quel que soit le nombre de cellules enparallèle. Dans une dernière partie ces lois de commande ont été testées sur un prototype en lesimplémentant sur FPGA afin de procéder à une vérification expérimentale / The parallel multilevel converters allow high current with a high power-weight ratio by associatingcommutation cells in parallel. This parallelization reduces the current in each cells and so onpermits to use standard range of components. With an adapted command the quality of the outputwaveforms is improved. This report will focus on a specific structure made off Buck converter withmagnetic coupling. Indeed thanks to the interleaved command, the output current ripple is reducedbut in return using separated inductances on each leg leads an increasing of the leg current ripple,directly linked to the number of leg and the ripple of the output current. In order to avoid thisproblem those inductances are replaced by one or more intercell transformers (ICT) that reducethe ripple of each leg current. However in a way to ensure unsaturated ICTs and good integrationit is necessary to balance the current of each leg despite parameter variation. Thus this report isfocused on modeling uncoupling methods for the system ensuring an equal distribution of thecurrents with duty cycles differences. Those modeling methods were generalized to achieve to analgorithm which generate control law whatever the number of leg. In the last part those controllaws are tested on a test bench by implementing them on a FPGA board to validate experimentallythe results

Les structures de conversion multiniveaux permettent de convertir en moyenne tension et forte puissance. Celles-ci sont construites à partir de cellules de commutations et permettent d’augmenter le courant et la tension en entrée ou en sortie. Ces structures sont appelées multiniveaux car les formes d’ondes des tensions en sortie permettent d’avoir plus de deux niveaux de tension différents. Les différentes structures peuvent être classées dans différentes catégories tel que la mise en série de pont en H, les convertisseurs multicellulaires série ou parallèle ou encore les structures utilisant le fractionnement du bus continu. Toutes ces structures ont des propriétés et applications différentes, même si certaines structures ont des propriétés communes. Il est aussi possible de créer de nouvelles structures en mixant les différentes structures de bases des différentes familles de convertisseurs multiniveaux ou en assemblant les structures de base de la conversion statique. Même si l’utilisation de structure de conversion multiniveaux permet de convertir à forte puissance, celle-ci n’est pas toujours aisée. En effet l’augmentation du nombre de niveaux ou de la tension d’entrée implique également une augmentation du nombre de composants semiconducteurs. Ceci peut être un frein à l’utilisation de convertisseur multiniveaux. Pour cela une nouvelle structure utilisant des composants partagés entre les différentes phases est proposée afin de limiter leur nombre. Un autre problème important lié aux convertisseurs multiniveaux est l’équilibrage des tensions des condensateurs du bus continu si celui-ci est composé de plus de deux condensateurs mis en série. Pour cela plusieurs solutions sont possibles : soit en utilisant une commande spécifique utilisant la modulation vectorielle, soit en utilisant des structures auxiliaires qui ont pour but d’équilibrer les différentes tensions des condensateurs. Dans une dernière partie ont été proposées de nouvelles structures qui permettent à la fois d’augmenter le courant de sortie et la tension en entrée en utilisant les principes des structures de base des convertisseurs multicellulaires série et parallèle. De plus, ces structures ont des propriétés intéressantes sur les formes d’ondes de sortie. De ces structures a été conçu un prototype permettant de valider les résultats de simulation. Une commande numérique implantée sur FPGA a été réalisée et a permis d’avoir des résultats expérimentaux intéressants. / This PhD Thesis deals with the study of new multilevel structures. At the beginning of this work, a new methodology to create new multilevel structures has been conceived. To evaluate the performances of these structures, there are many possibilities: number of output voltage levels, number of components, and the quality of the converters’ output waveforms. The list of criteria is not exhaustive. One technique to obtain an output multilevel waveform is to split the DC link in several capacitors. There is a limitation since putting more than two capacitors in serial connection leads to an unbalancing of these voltage capacitors. Several solutions are possible to balance these voltages. The first one uses the control of the structure in a three phase application, using a space vector modulation and minimizing the energy stored in the DC link. The second solution consists in using auxiliary circuits, which realize an energy transfer between one capacitor to another through an inductor. The drawback of this method is the high number of components. This problem can be reduced sharing some components between the three phases of the converter. The third part of this study is related to multicell converters, structures with very interesting good properties. New converter structures mix serial and parallel multicell converters, to obtain a hybrid converter with similar performances to the two basic converters. An experimental prototype was built to validate the results of the PhD. The digital control of this hybrid structure was made with a FPGA where two DSP processors were implemented.