In recent high-speed digital circuits, the simultaneous switching noise (SSN) or ground bounce noise (GBN) is induced due to the transient currents flowing between power and ground planes during the state transitions of the logic gates. In order to¡@analyze the effect of GBN on power delivery systems effectively and accurately, the impedance of power/ground is an important index to evaluate power delivery systems. In the operating frequency bandwidth, the power impedance must be less than the target impedance. The typical way to suppress the SSN is adding decoupling capacitors to create a low impedance path between power and ground planes. By using the admittance matrix method, we can evaluate the effect of decoupling capacitors mounted on PCB fast and accurately reducing the time needed from the empirical or try-and-error design cycle. In order to reduce the cost of decoupling capacitors, the genetic algorithm is employed to optimize the placement of decoupling capacitors to suppress the GBN. The decoupling capacitor are not effective in the GHz frequency range due to their inherent lead inductance. The electromagnetic bandgap(EBG) structure can produce a stopband to prevent the noise from disperseing at higher frequency. Combining decoupling capacitors with EBG structure to find the optimum placement for suppression of the SSN by using the genetic algorithm.

On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors [4]. They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decap’s area, a new active decap design is proposed for 90 nm technology.

The operation speed of power delivery system of packages has been upgraded to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power plane and the ground plane, then to produce the programs of electromagnetic interference. In this thesis, we will analyze the EMI of power delivery system of packages by finite-difference time-domain in two dimensions structure in three sections. In firist section, to computing EMI in finite-difference time-domain in two dimensions structure. In second section, to analyze more complicated power delivery plane, ex: EBG, in finite-difference time-domain in two dimensions structure. In three section, to add property of capacitors on power plane to reduce EMI in two dimensions structure. Above all, we hope to built a fast computing method to compute EMI to solve the time-consuming problems of full-wave simulated software. And to supply the engineer to deal with the similar problems in packages efficiently.

In recent high-speed digital circuits with pico-second rising/falling edges, it is reasonable to consider the power/ground planes as a dynamic electromagnetic system. The simultaneous switching noise (SSN) or ground bounce noise (GBN), resulting from the transient currents which flow between power/ground planes during the state transitions of the logic gates, has become a critical factor to degrade the signal integrity (SI) and power integrity (PI) in PCB or package design. In order to accurately perform overall system-level power integrity simulation, extracting the SPICE-compatible models with the resonant effect being considered in the power/ground planes and incorporating the model into the conventional circuit simulator, such as SPICE, is essential. In this thesis, a two-dimensional transmission line (2D-TL) model is proposed for constructing the SPICE-compatible model of the power/ground planes. Based on this model, the ground bounce noise for the BGA package mounted on a PCB can be efficiently evaluated. It is found that the behavior of GBN between the only package and package mounted on a PCB (hybrid structure) is obvious different. Then, we combine the SPICE-compatible model of the power/ground planes with decoupling capacitors to fast evaluate the behavior of GBN. It also has a good agreement between our model and the measured result. Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequency higher than GHz due to their inherent lead inductance. In recent, a new method for eliminating the GBN at higher frequency is proposed by electromagnetic bandgap (EBG) structure with high impedance surface (HIS). Finally, we utilize 2D-TL model to fast analyze the behavior of the EBG, and combine decoupling capacitors with EBG structure to research the suppression of the GBN.

The operation speed of modern computer system has been upgraded from several hundred MHz to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power and ground plane, so called ¡§Ground bounce.¡¨ To prevent the ground bounce from IC operation, decoupling capacitors are used. In this thesis, an efficient numerical approach which is based on the two-dimensional (2D) finite-difference time-domain (FDTD) method and with a new recursive algorithm has been used for modeling the power/ground planes characteristics with SMT capacitors above them. By the way, we take several methods, such as Debye model, FDTD-SPICE, and telegrapher¡¦s equation, for modeling various mother board structures. Finally, we use the genetic algorithm for calculating the optimum capacitor placements to meet the expect ground bounce limitation.