In the current transmission systems, the transmission capacity is still not enough. The information bandwidth of the optical fiber communication system is limited by the optical amplifier bandwidth, and more efficient use of the bandwidth is a very important issue. Therefore, the amplitude and phase shift keying (APSK) is one attractive method of multi-bit per symbol modulation scheme to improve the spectral efficiency, and it can effectively increase the transmission capacity. To improve the capacity and the spectral efficiency, the advanced modulation format is effective, and the coherent detection scheme is also effective. However, an optical phase-locked loop (PLL) to lock the local oscillator (LO) phase and the signal phase required for the homodyne detection is still difficult to realize and it makes the receiver circuit complicated. Using the digital coherent receiver, the optical carrier phase information can be recovered by means of the digital signal processing (DSP), and this scheme enables to eliminate the optical PLL circuit by the phase estimation algorithm through the DSP. The stored data can be offline processed by using the MATLAB program. This master thesis is focusing on studying the transmission performance of the APSK format using the DSP in the digital coherent receiver. 497km transmission experiment has been conducted. Subsequently, the stored data are offline processed by the algorithms of the DSP. Then, the APSK performances between back-to-back and 497km transmission are compared.

The coherent optical fiber communication technology is attracting significant attentions in the world, because it can realize the spectrally efficient transmission system. One major difference between 1980¡¦s and the latest coherent technology is the utilization of the digital signal processing (DSP). In 1980¡¦s the optical phase locked loop (OPLL) was required to realize the homodyne detection, and it was significantly difficult to realize. The latest coherent technology utilizes the DSP in place of the OPLL to realize the homodyne detection, and it is much easier than the OPLL. The real-time realization of the DSP is still a problem. Because the DSP uses software to process the signal, it needs an extreme calculation power for the high-speed communication system. People always utilize the field programmable gate array (FPGA) to realize the real-time DSP, but the cost of the FPGA is too expensive for the commercial system at this moment. This master thesis intend to utilize commercially available personal computer (PC) contained a GPU calculation board to replace FPGA. It can reduce the cost of the coherent receiver. Also, this receiver is defined by the software rather than the hardware. It means that we can realize a flexible receiver defined by the software.

This thesis presented a sensor-less permanent magnet synchronous motor (PMSM) driver for controlling air-conditioner rotary compressor speed. In this thesis, a quasi-sine pulse-width modulation (PWM) driving method was proposed. Furthermore, the current feedback control scheme and rotor magnet pole position detection were included. The system structure was implemented by using a digital signal processing (DSP) platform. The proposed driving scheme was compared with the square-wave driving without current feedback and six-step square-wave driving method with current feedback. Moreover, the passive and shunt semi-active power factor correction (PFC) technique were researched for the air-conditioner application. Experimental results demonstrated that the system power factor could be improved by the proposed shunt semi-active PFC method. Besides, the proposed sensor-less quasi-sine PWM driving method implemented in an air-conditioner compressor driver was capable of reducing the magnitude of rotational speed ripples, compressor vibration, and system power consumption.

The design and implementation of the digital signal processing (DSP) based on a brushless DC (BLDC) motor sensorless driver with Sine PWM. Because of dispensable power consumption problems generated by closed-loop speed control methods with speed estimation signal feedback are adopted for improvement. In addition, current feedback is added to the driver for the sake of increasing efficiency. Then, sine wave closes 30¢X, 15¢X, and 8¢X to comparing the improvements for efficiency. Experimental results from a laboratory prototype are shown to verify the feasibility of the proposed scheme. The laboratory results show that current feedback and sine wave closed 8¢X have high efficiency.

<p>This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. </p><p>The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. </p><p>The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms. </p><p>The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.</p>

This report presents improved architecture designs and implementations for a fused floating-point add-subtract unit. The fused floating-point add-subtract unit is useful for DSP applications such as FFT and DCT butterfly operations. To improve the performance of the fused floating-point add-subtract unit, the dual path algorithm and pipelining technique are applied. The proposed designs are implemented for both single and double precision and synthesized with a 45nm standard-cell library. The fused floating-point add-subtract unit saves 40% of the area and power consumption and the dual path fused floating-point add-subtract unit reduces the latency by 30% compared to the traditional discrete floating-point add-subtract unit. By combining fused operation and the dual path design, the proposed floating-point add-subtract unit achieves low area, low power consumption and high speed. Based on the data flow analysis, the proposed fused floating-point add-subtract unit is split into two pipeline stages. Since the latencies of two pipeline stages are fairly well balanced the throughput of the entire logic is increased by 80% compared to the non-pipelined implementation. / text

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Στην παρούσα διπλωματική αναπτύχθηκε μια μέθοδος ψηφιακής επεξεργασίας σημάτων για ακουστικά σήματα συμβατή με πραγματικού χρόνου επεξεργασία. Αρχικά έγινε περίληψη των λειτουργιών των επεξεργαστών ειδικού σκοπου. Έγινε μελέτη της ανάλυσης στο πεδίο της συχνότητας καθώς και της συνάρτησης συνεκτικότητας. Για τους σκοπούς της διπλωματικής υλοποιήθηκε αλγόριθμος αφαίρεσης θορύβου από σήματα ομιλίας που αξιοποιεί την συνάρτηση συνεκτικότητας και χρησιμοποιεί είσοδο από δύο μικρόφωνα. Ο αλγόριθμος αυτός υλοποιήθηκε και δοκιμάστικε σε μη-πραγματικό χρόνο σε μαθηματικό λογισμικό , καθώς και σε πραγματικό χρόνο σε επεξεργαστή ειδικού σκοπού. / In this thesis, a method of digital signal processing for acoustic signals was developed, compatible with real-time processing. At first, a review of the operations that special purpose digital signal processors feature. We also studied the frequency domain analysis and the coherence function in depth. For the purposes of this thesis an algorithm of noise reduction from speech signals was implemented, that exploits the coherence function and takes two microphone signals as inputs. The algorithm was implemented offline in a mathematical software, as well as real time in a special purpose digital signal processor.

The Generalized Sidelobe Canceller is an adaptive algorithm for optimally estimating the parameters for beamforming, the signal processing technique of combining data from an array of sensors to improve SNR at a point in space. This work focuses on the algorithm’s application to widely-separated microphone arrays with irregular distributions used for human voice capture. Methods are presented for improving the performance of the algorithm’s blocking matrix, a stage that creates a noise reference for elimination, by proposing a stochastic model for amplitude correction and enhanced use of cross correlation for phase correction and time-difference of arrival estimation via a correlation coefficient threshold. This correlation technique is also applied to a multilateration algorithm for an efficient method of explicit target tracking. In addition, the underlying microphone array geometry is studied with parameters and guidelines for evaluation proposed. Finally, an analysis of the stability of the system is performed with respect to its adaptation parameters.