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The delivery of health care services has been under pressure due to limited funding and increasing demand. This has highlighted the need to increase not only the effectiveness but also the efficiency of health care delivery. Discrete-event simulation has been suggested as an analysis tool in health care management to support the planning of health care resources. The overall purpose of this thesis is to investigate the possibilities and requirements for using discrete-event simulation in analyzing and planning the use of hospital resources. This is achieved by three case studies that focus on improvements in patient flow of emergency patients that require a radiology examination, intensive care unit capacity planning and operating room allocation strategies, respectively. The first case investigates the current stage of digitization and process orientation in hospital care as a prerequisite for efficient process simulation and analysis. The study reveals an emergency-radiology patient flow process that is not very well measured and uncovers disparate information systems storing incompatible and fragmented data. These results indicate that the current degree of process orientation and the current IT infrastructure does not enable efficient use of quantitative process analysis and management tools like simulation. In the second case the possibilities to develop generic hospital unit simulation models by building and validating a generic intensive care unit (ICU) model are explored. The results show that some of the modeling approaches described in literature cannot replicate the actual behavior observed in all studied ICUs. It is important to identify patient groups for different admission priorities, to account for over-utilizations in the model logic, and to discover and properly model dependencies in the input data. The research shows that it is possible to develop a generic ICU simulation model that could realistically describe the performance of different real ICUs in terms of occupancy, coverage and transfers. The value of simulation modeling in health care management is examined in the third case through the development and use of a simulation model for optimal resource allocation and patient flow in a hospital operating department. The goal of the simulation modeling in this case was to identify bottlenecks in the patient flow and to try different alternatives for allocation of operating room capacity in order to increase the utilization of operating room resources. The final model was used to evaluate four different proposed changes to operating room time allocation.

This simulation study was carried out at a company in the automotive industry. In their factory, the company manufactures gearboxes, where the gearbox assembly is one step in the manufacturing process. In the main assembly line, many different gearbox variants are manufactured, each with its own cycle time in the different assembly stations. Due to this variation in cycle times the throughput in the main assembly line can fluctuate depending on which gearbox variants are produced. To maintain a desired throughput a tool for forecasting the throughput would be of great value to the company. Due to the large number of gearbox variants, the company also experiences difficulties understanding if there are stations in the assembly which are recurring bottlenecks. The purpose of this project is to create a tool that can forecast the daily throughput of the main assembly line and identify bottlenecks in the main assembly line. The purpose is also to investigate whether some stations often are bottleneck stations during a certain period. The model evaluation was based on validation of input-output-transformation. A bottleneck analysis based on the active times of the stations was carried out with the best-performing model. The best-performing model version resulted in 68 percent valid forecasts for the 57 historical production days. The forecasts were valid for all historical production days which were Mondays, Tuesdays, Wednesdays, and Thursdays. For Fridays and Sundays, 25 and 0 percent were valid, respectively. A bottleneck analysis was carried out for 37 historical production days where the result showed that, based on the share of active time, a single station was identified as the bottleneck station for all days. The difference between the bottleneck station’s share of active time and other stations’ share of active time was deemed small enough to be within the error margin. Additionally, the queues in the main assembly line indicated that the bottleneck was located within another group of stations. Due to the ambiguity of the results, the conclusion drawn was that the main assembly line did not experience any clear bottleneck station during the 37 historical production days. / <p>Examensarbetet är utfört vid Institutionen för teknik och naturvetenskap (ITN) vid Tekniska fakulteten, Linköpings universitet</p>

This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. / This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We first introduce the sampled-data setting from Wang, and then define the sampled-data properties he identified, including the SD controllability property. We then introduce Wang's formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We then discuss Wang's modular and centralized translation method. We next introduced new modular results for the SD controllability point 3.1, SD controllability point 3.2, SD controllability point 4, activity loop free and S-singular prohibitable behaviour that allow one to verify the properties using only a portion of the system, instead of having to construct the entire system model. This should allow faster verification times as well as allow larger systems to be verified. We then introduce for the first time algorithms to verify Wang's CS Deterministic and non self-loop ALF properties. The remainder of the thesis focuses on developing algorithms and software to automatically convert a TDES first into an FSM, and then into a VERILOG module. VERILOG is a hardware description language which allows our FSM to be compiled and implemented on digital logic devices such as an FPGA. We then tested our method by modelling a simple door locking system as TDES, checking that the system satisfies the required sampled-data properties, and then translating the result into VERILOG. The above algorithms and methods have all been implemented as a part of the graphical DES research tool, DESpot. / Thesis / Master of Computer Science (MCS)