With increasing demands on mobile communication transfer rates the circuits in mobile phones must be designed for higher performance while maintaining low power consumption for increased battery life. One possible way to improve an existing architecture is to implement instruction prefetching. By predicting which instructions will be executed ahead of time the instructions can be prefetched from memory to increase performance and some instructions which will be executed again shortly can be stored temporarily to avoid fetching them from the memory multiple times. By creating a trace driven simulator the existing hardware can be simulated while running a realistic scenario. Different methods of instruction prefetch can be implemented into this simulator to measure how they perform. It is shown that the execution time can be reduced by up to five percent and the amount of memory accesses can be reduced by up to 25 percent with a simple loop buffer and return stack. The execution time can be reduced even further with the more complex methods such as branch target prediction and branch condition prediction.

This thesis proposes an optimized Co-ordinate Rotation Digital Computer (CORDIC) algorithm in the rotation and extended vectoring mode of the circular co-ordinate system. The CORDIC algorithm computes the values of trigonometric functions and their inverses. The proposed algorithm provides the result with a lower overall latency than existing systems. This is done by using redundant representations and approximations of the required direction and angle of each rotation. The algorithm has been designed to provide the result in a fixed number of iterations $n$ for the rotation mode and $3\lceil n/2 \rceil + \lfloor n/2 \rfloor$ for the extended vectoring mode; where, $n$ is a design parameter. In each iteration, the algorithm performs between 0 and $p/n$ parallel rotations, where, $p$ is the number of precision bits and $n$ is the selected number of iterations. A technique to handle the scaling factor compensation for such an algorithm is proposed. The results of the functional verification for different values of $n$ and an estimation of the overall latency are presented. Based on the results, guidelines to choosing a value of $n$ to meet the required performance have also been presented.

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Traditional communication hardware has focused on modular architectures. Now, with the incoming high speed DSP and FPGAs a shift from traditional modular architecture to reconfigurable architecture has taken place. The nature of this architecture allows to optimize various telemetry applications in a single platform. This paper describes a reconfigurable multi channel communication system.

Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated. In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures. A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.

The ease with which indoor wireless systems can be installed has become their main selling feature. A desirable application for wireless systems is the transmission of compressed digital music in an indoor shopping mall environment. The indoor environment, with its many walls and highly reflective surfaces, has a high level of multipath. High levels of slowly changing multipath can cause deep fades, and therefore reduce the reliability of the system. <p> The proper use of multiple receiving elements is one way to mitigate the deep fades caused by multipath. The main objective of this thesis is to study a simple and cost effective approach to combining the signals from several receiving elements. A novel diversity combining approach using 2 receiving elements is presented. The novel diversity combining approach consists of periodically changing the phase of one of the two received signals. <p> A set of simulations was developed to study the effectiveness of the novel diversity combining method in mitigating deep multipath fades. The relative performances of two different implementations of the diversity combining were compared to a baseline test case that did not include diversity combining. In both of the simulated implementations, the diversity combining approach proved to be an effective means of mitigating the multipath fading phenomenon. <p> A proof-of-concept, bench-top hardware prototype was also developed. The transmitter and receiver were implemented in Field Programmable Gate Arrays (FPGAs). The laboratory testing of the hardware successfully illustrated the feasibility of the proof-of-concept system.

The ease with which indoor wireless systems can be installed has become their main selling feature. A desirable application for wireless systems is the transmission of compressed digital music in an indoor shopping mall environment. The indoor environment, with its many walls and highly reflective surfaces, has a high level of multipath. High levels of slowly changing multipath can cause deep fades, and therefore reduce the reliability of the system. <p> The proper use of multiple receiving elements is one way to mitigate the deep fades caused by multipath. The main objective of this thesis is to study a simple and cost effective approach to combining the signals from several receiving elements. A novel diversity combining approach using 2 receiving elements is presented. The novel diversity combining approach consists of periodically changing the phase of one of the two received signals. <p> A set of simulations was developed to study the effectiveness of the novel diversity combining method in mitigating deep multipath fades. The relative performances of two different implementations of the diversity combining were compared to a baseline test case that did not include diversity combining. In both of the simulated implementations, the diversity combining approach proved to be an effective means of mitigating the multipath fading phenomenon. <p> A proof-of-concept, bench-top hardware prototype was also developed. The transmitter and receiver were implemented in Field Programmable Gate Arrays (FPGAs). The laboratory testing of the hardware successfully illustrated the feasibility of the proof-of-concept system.

Uppgiften består i att konstruera och designa en DSP lösning för att förebygga stamning. Genom att en signal tas in på en mikrofon och bearbetas i en DSP därefter skickas ut på en hörlur. Signalen som behandlas i DSP:n ska frekvenshöjas och fördröjas. Pitch och fördröjning ska kunna justeras m.h.a. en omkopplare. Till hjälp fanns utvecklingskortet eZdspF2808 från Texas Instruments och en in/utgångsförstärkare. Tidigare erfarenheter av DSP från Texas Instruments saknades. Att lära känna utvecklingskortet var därför en del av arbetet. Det bestod mest i att läsa användarguider från Texas Instruments hemsida. Utvecklingskortet saknar en DA-omvandlare, en sådan konstruerades. / This thesis describes a system that uses DSP technology to reduce stuttering. One eZdspF2808 development card is used as a test platform. The lack of a DA-converter forced us to construct our own. A software algorithm producing a delay and a pitch was implemented in DSP C programming language.

This thesis presents a systematic and structured way to migrate embedded software running on a digital signal processor to a different hardware platform. The solution includes using design patterns, a layered architecture and clearly defined interfaces to perform hardware abstraction. The proposed solution is aimed for a particular embedded system used in a product at AI.

The aim of this thesis is to design a controllable DC-link output voltage for isolated slotless tubular linear generators (STLG), which is capable of directly harnessing wave and solar thermal energies. For supplying stable DC-link voltage to load, a suitable voltage regulation circuit is designed based on the integrate system performance assessment. Electrical and mechanical parameters in this refined STLG design are involved to analyze the operational behaviors through magnetic equivalent circuit analysis at different operating modes. From the theoretical modeling and experimental results, both the AC-side and DC-side properties of generator outputs can then be thoroughly investigated. Finally, based on the performance of controllable rectifier model, a three-phase PWM rectifier has been established, and then the regulated DC-link voltage can be implemented using a DSP-based controller combined with required peripheral circuits.

This thesis is to design a DSP-based speed-sensorless driver for an induction motor. The driver schemed with closed loop constant V/F ratio is used as the speed control configuration, and a new integrator with adaptive compensation is derived to estimate motor speed. The developed driver with speed estimator has solved the problems of estimation deviation and stability which was occurred when designed by Indirectly Field Orientation Control method under low speed by 10% of rated speed. The experiments demonstrate the sensorless driver has performance of accuracy and efficiency for speed estimation when motor is operated under the circumstance of low speed range and parameter variation.