Zhao Fei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 87-89). / Abstracts in English and Chinese. / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Multirate Scheme --- p.2 / Chapter 1.1.1 --- VSF Scheme --- p.3 / Chapter 1.1.2 --- Multicode Scheme --- p.5 / Chapter 1.2 --- Multicode CDMA System --- p.7 / Chapter 1.2.1 --- System Model --- p.7 / Chapter 1.2.2 --- Envelope Variation of Multicode Signal --- p.9 / Chapter 1.2.3 --- Drawback of Multicode Scheme --- p.11 / Chapter 1.3 --- Organization of the Thesis --- p.13 / Chapter 2. --- Related Work on Minimization of PAP of Multicode CDMA --- p.15 / Chapter 2.1 --- Constant Amplitude Coding --- p.16 / Chapter 2.2 --- Multidimensional Multicode Scheme --- p.22 / Chapter 2.3 --- Precoding for Multicode Scheme --- p.25 / Chapter 2.4 --- Summary --- p.26 / Chapter 3. --- Multicode CDMA System with Constant Amplitude Transmission --- p.27 / Chapter 3.1 --- System Model --- p.28 / Chapter 3.2 --- Selection of Hadamard Code Sequences --- p.31 / Chapter 3.3 --- The Optimal Receiver for the Multicode System --- p.37 / Chapter 3.3.1 --- The Maximum-Likelihood Sequence Detector --- p.38 / Chapter 3.3.2 --- Maximum A Posteriori Probability Detector --- p.41 / Chapter 4. --- Multicode CDMA System Combined with Error-Correcting Codes --- p.45 / Chapter 4.1 --- Hamming Codes --- p.46 / Chapter 4.2 --- Gallager's Codes --- p.48 / Chapter 4.2.1 --- Encoding of Gallager's Codes --- p.48 / Chapter 4.2.2 --- Multicode Scheme combined with Gallager's Code --- p.52 / Chapter 4.2.3 --- Iterative Decoding of the Multicode Scheme --- p.55 / Chapter 4.3 --- Zigzag Codes --- p.59 / Chapter 4.4 --- Simulation Results and Discussion --- p.62 / Chapter 5. --- Multicode CDMA System with Bounded PAP Transmission --- p.68 / Chapter 5.1 --- Quantized Multicode Scheme --- p.69 / Chapter 5.1.1 --- System Model --- p.69 / Chapter 5.1.2 --- Interference of Code Channels --- p.71 / Chapter 5.2 --- Parallel Multicode Scheme --- p.74 / Chapter 5.2.1 --- System Model --- p.74 / Chapter 5.2.2 --- Selection of Hadamard Code Sequences --- p.75 / Chapter 6. --- Conclusions and Future Work --- p.82 / Chapter 6.1 --- Conclusions --- p.82 / Chapter 6.2 --- Future Work --- p.84 / Bibliography --- p.87

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Eliezer Menahem Gafni. / Ph.D.

The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.

Thesis (Ph. D.)--University of Missouri-Columbia, 2000. / Typescript. Vita. Includes bibliographical references (leaves 110-114). Also available on the Internet.

Thesis (Ph. D.)--University of Missouri-Columbia, 2000. / Typescript. Vita. Includes bibliographical references (leaves 110-114). Also available on the Internet.

We have investigated, in various multiple senses, the “capacity” of several models of erasure networks. The defining characteristic of a memoryless erasure network is that each channel between any two nodes is an independent erasure channel. The models that we explore differ in the absence or presence of interference at either the transmitters, the receivers, or both; and in the availability of feedback at the transmitters. The crux of this work involves the investigation and analysis of several different performance measures for these networks: traditional information capacity (including multicast capacity and feeback capacity), secrecy capacity, and transport capacity. / text

The rapid growth of wireless subscribers and services as well as the increased use of internet services, suggest that wireless internet access will increase rapidly over the next few years. This will require the provision of high data rate wireless communication services. However the problem of a limited and expensive radio spectrum coupled with the problem of the wireless fading channel makes it difficult to provide these services. For these reasons, the research area of high data rate, bandwidth efficient and reliable wireless communications is currently receiving much attention. Concatenated codes are a class of forward error correction codes which consist of two or more constituent codes. These codes achieve reliable communications very close to the Shannon limit provided that sufficient diversity, such as temporal or spatial diversity, is available. Space-time trellis codes (STTCs) merge channel coding and transmit antenna diversity to improve system capacity and performance. The main focus of this dissertation is on STTCs and concatenated STTCs in quasi-static and rapid Rayleigh fading channels. Analytical bounds are useful in determining the behaviour of a code at high SNRs where it becomes difficult to generate simulation results. A novel method is proposed to analyse the performance of STTCs and the accuracy of this analysis is compared to simulation results where it is shown to closely approximate system performance. The field of concatenated STTCs has already received much attention and has shown improved performance over conventional STTCs. It was recently shown that double concatenated convolutional codes in AWGN channels outperform simple concatenated codes. Motivated by this, two double concatenated STTC structures are proposed and their performance is compared to that of a simple concatenated STTCs. It is shown that double concatenated STTCs outperform simple concatenated STTCs in rapid Rayleigh fading channels. An analytical model for this system in rapid fading is developed which combines the proposed analytical method for STTCs with existing analytical techniques for concatenated convolutional codes. The final part of this dissertation considers a direct-sequencejslow-frequency-hopped (DSj SFH) code division multiple access (CDMA) system with turbo coding and multiple transmit antennas. The system model is modified to include a more realistic, time correlated Rayleigh fading channel and the use of side information is incorporated to improve the performance of the turbo decoder. Simulation results are presented for this system and it is shown that the use of transmit antenna diversity and side information can be used to improve system performance. / Thesis (M.Sc.Eng.)-University of Natal, Durban, 2002.

The Transmission Control Protocol (TCP) is the most widely used transport protocol in the Internet. TCP is a reliable transport protocol that is tuned to perform well in wired networks where packet losses are mainly due to congestion. Wireless channels are characterized by losses due to transmission errors and handoffs. TCP interprets these losses as congestion and invokes congestion control mechanisms resulting in degradation of performance. TCP is usually layered over the Internet protocol (lP) at the network layer. JP is not reliable and does not provide for any Quality of Service (QoS). The Internet Engineering Task Force (IETF) has provided two techniques for providing QoS in the Internet. These include Integrated Services (lntServ) and Differentiated Services (DiffServ). IntServ provides flow based quality of service and thus it is not scalable on connections with large flows. DiffServ has grown in popularity since it is scalable. A packet in a DiffServ domain is classified into a class of service according to its contract profile and treated differently by its class. To provide end-to-end QoS there is a strong interaction between the transport protocol and the network protocol. In this dissertation we consider the performance of the TCP over a wireless channel. We study whether the current TCP protocols can deliver the desired quality of service faced with the challenges they have on wireless channel. The dissertation discusses the methods of providing for QoS in the Internet. We derive an analytical model for TCP protocol. It is extended to cater for the wireless channel and then further differentiated services. The model is shown to be accurate when compared to simulation. We then conclude by deducing to what degree you can provide the desired QoS with TCP on a wireless channel. / Thesis (M.Sc.Eng.)-University of Natal, Durban, 2001.

The objective of this dissertation is to investigate both the theoretical and practical aspects of redundancy elimination methods in data networks. Redundancy elimination provides a powerful technique to improve the efficiency of network links in the face of redundant data. In this work, the concept of network compression is introduced to address the redundancy elimination problem. Network compression aspires to exploit the statistical correlation in data to better suppress redundancy. In a nutshell, network compression enables memorization of data packets in some nodes in the network. These nodes can learn the statistics of the information source generating the packets which can then be used toward reducing the length of codewords describing the packets emitted by the source. Memory elements facilitate the compression of individual packets using the side-information obtained from memorized data which is called ``memory-assisted compression''. Network compression improves upon de-duplication methods that only remove duplicate strings from flows. The first part of the work includes the design and analysis of practical algorithms for memory-assisted compression. These algorithms are designed based on the theoretical foundation proposed in our group by Beirami et al. The performance of these algorithms are compared to the existing compression techniques when the algorithms are tested on the real Internet traffic traces. Then, novel clustering techniques are proposed which can identify various information sources and apply the compression accordingly. This approach results in superior performance for memory-assisted compression when the input data comprises sequences generated by various and unrelated information sources. In the second part of the work the application of memory-assisted compression in wired networks is investigated. In particular, networks with random and power-law graphs are studied. Memory-assisted compression is applied in these graphs and the routing problem for compressed flows is addressed. Furthermore, the network-wide gain of the memorization is defined and its scaling behavior versus the number of memory nodes is characterized. In particular, through our analysis on these graphs, we show that non-vanishing network-wide gain of memorization is obtained even when the number of memory units is a tiny fraction of the total number of nodes in the network. In the third part of the work the application of memory-assisted compression in wireless networks is studied. For wireless networks, a novel network compression approach via memory-enabled helpers is proposed. Helpers provide side-information that is obtained via overhearing. The performance of network compression in wireless networks is characterized and the following benefits are demonstrated: offloading the wireless gateway, increasing the maximum number of mobile nodes served by the gateway, reducing the average packet delay, and improving the overall throughput in the network. Furthermore, the effect of wireless channel loss on the performance of the network compression scheme is studied. Finally, the performance of memory-assisted compression working in tandem with de-duplication is investigated and simulation results on real data traces from wireless users are provided.

With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.