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The design and development of technology applications has to deal with many variables. Reference is obviously made to established hardware and software support, particularly with regard to the choice of appropriate operating systems, development model, environment and programming language. With the growth of networked and web-exposed systems, we are increasingly dealing with IoT (Internet-of-Things) systems: complex applications consisting of a network of often heterogeneous elements to be managed like an orchestra, using existing elements and creating new ones. Among the many fields affected by this phenomenon, two in particular are considered here: industry and medical, key sectors of modern society. Given the inherently parallel nature of such networks and the fact that it is commonly necessary to manage them via the Web, the most prevalent de facto model employs an architecture relying on a paradigm based on data flows, representing the entire system as a kind of assembly line in which each entity acquires input data and returns an output in a perfectly asynchronous manner. This thesis highlights some notable limitations of this approach and proposes an evolution that resolves some key issues. This has been done not only on a purely theoretical level, but with actual implementations currently operational and thus demonstrated in the field. Rather than proposing an abstract formalisation of a new solution, the basic principles of a whole new architecture are presented here instead, going into more detail on some key features and with experimental and practical feedback implemented as a full blown software platform. A first contribution is the definition of the principles of a new programming architecture, disseminated with some published articles and a speech in an international congress. A second contribution concerns a lightweight data synchronisation strategy, which is particularly useful for components that need to continue working during offline periods. A third contribution concerns a method of storing a symmetric encryption key combined with a peculiar retrieval and verification technique: this has resulted in an international patent, already registered. A fourth contribution concerns a new data classification model, which is particularly effective for processing information asynchronously. Issues related to possible integrations with artificial intelligence systems have also been addressed, for which a number of papers are being written, introduced by a presentation that has just been published.

As SystemC gains popularity as a System Level Design Language (SLDL) for System-On-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, all SystemC models employ a Discrete-Event simulation kernel making it difficult to express most MOCs without specific designer guidelines. This often makes it unnatural to express different MOCs in SystemC. For the simulation framework, this sometimes results in unnecessary delta cycles for models away from the Discrete-Event MOC, hindering the simulation performance of the model. Our goal is to extend SystemC's simulation framework to allow for better modelling expressiveness and efficiency for the Synchronous Data Flow (SDF) MOC. The SDF MOC follows a paradigm where the production and consumption rates of data by a function block are known a priori. These systems are common in Digital Signal Processing applications where relative sample rates are specified for every component. Knowledge of these rates enables the use of static scheduling. When compared to dynamic scheduling of SDF models, we experience a noticeable improvement in simulation efficiency. We implement an extension to the SystemC kernel that exploits such static scheduling for SDF models and propose designer style guidelines for modelers to use this extension. The modelling paradigm becomes more natural to SDF which results to better simulation efficiency. We will distribute our implementation to the SystemC community to demonstrate that SystemC can be a heterogeneous SLDL. / Master of Science

In the past, various approaches to the high performance numerical computing problem have been explored. Recently, researchers have begun to explore the possibilities of using Field Programmable Gate Arrays (FPGAs) to solve numerically intensive problems. FPGAs offer the possibility of customization to any given application, while not sacrificing applicability to a wide problem domain. Further, the implementation of data flow graphs directly in silicon makes FPGAs very attractive for these types of problems. Unfortunately, current FPGAs suffer from a number of inadequacies with respect to the task. They have lower transistor densities than ASIC solutions, and hence less potential computational power per unit area. Routing overhead generally makes an FPGA solution slower than an ASIC design. Bit-oriented computational units make them unnecessarily inefficient for implementing tasks that are generally word-oriented. And finally, in large volumes, FPGAs tend to be more expensive per unit due to their lower transistor density. To combat these problems, researchers are now exploiting the unique advantage that FPGAs exhibit over ASICs: reconfigurability. By customizing the FPGA to the task at hand, as the application executes, it is hoped that the cost-performance product of an FPGA system can be shown to be a better solution than a system implemented by a collection of custom ASICs. Such a system is called a Configurable Computing Machine (CCM). Many aspects of the design of the FPGAs available today hinder the exploration of this field. This thesis addresses many of these problems and presents the embodiment of those solutions in the Colt CCM. By offering word grain reconfiguration and the ability to partially reconfigure at computational element resolution, the Colt can offer higher effective utilization over traditional FPGAs. Further, the majority of the pins of the Colt can be used for both normal I/O and for chip reconfiguration. This provides higher reconfiguration bandwidth contrasted with the low percentage of pins used for reconfiguration of FPGAs. Finally, Colt uses a distributed reconfiguration mechanism called Wormhole Run-Time Reconfiguration (RTR) that allows multiple data ports to simultaneously program different sections of the chip independently. Used as the primary example of Wormhole RTR in the patent application, Colt is the first system to employ this computing paradigm. / Ph. D.

The growth of high performance computing to date can largely be attributed to continuing breakthroughs in materials and manufacturing.In order to increase computing capacity beyond these physical bounds, new computing paradigms must be developed that make more efficient use of existing manufacturing technologies. Custom Computing Machines (CCMs) are an emerging class of computers that offer promising possibilities for future high-performance computational needs. With the increasing popularity of the run-time reconfigurable (RTR) concept in the CCM community, questions have arisen as to what computational device should be at the heart of an RTR platform. Currently the preferred device, and really the only practical device, has been the RAM-based Field-Programmable Gate Array (FPGA). Unfortunately, for applications that require high performance, FPGAs are limited by their narrow data path and small computational density. The Colt integrated circuit has been designed from the start to be the computational processing element in an RTR platform. Colt is an RTR data-flow processor array with a course-grain architecture (16-bit data path). This thesis covers the VLSI implementation and verification of the Colt integrated circuit, including the approach and methods necessary to make a functionally working integrated circuit. / Master of Science

In an era where the network of interconnected devices is rapidly expanding, it is difficult for organizations to adapt to the increasingly data-rich and dynamic environment while remaining competitive. Employees experience that much of their time and resources is spent daily on repetitive, inefficient and mundane tasks. Whereas lean manufacturing has manifested itself as a well-known optimization concept, lean information management and the removal of waste is not yet being used to its full potential as its direct value is less visible. A case study was conducted to define which types of non-value adding activities can be identified within information flows and to determine whether decentralized application development can eliminate this digital waste. An internal information flow was modelled, analyzed and optimized by developing customized applications on the Microsoft Power Platform. Based on literature from the field of manufacturing and software development, a framework was developed to categorize digital waste as well as higher order root causes in terms of business strategy and IT infrastructure. While decentralized app development provides the ability to significantly reduce operational digital waste in a simplified manner, it can also enable unnecessary expansion of a common data model and requires application lifecycle management efforts as well as edge security to ensure data compliance and governance. Although limited to one case study, the suggested framework could give insights to organizations that aim to optimize internal workflows by identifying and eliminating digital waste and its root causes. / I en tid där nätverk av sammankopplade enheter expanderar snabbt, är det svårt för organisationer att anpassa sig till den allt mer datoriserade och dynamiska miljön och samtidigt förbli konkurrenskraftiga. Anställda upplever att mycket av deras tid och resurser spenderas på repetitiva, ineffektiva och vardagliga uppgifter. Lean manufacturing har visat sig vara ett välkänt optimeringskoncept, dock har informationshantering och avlägsnande av slöseri inte ännu nått sin fulla potential eftersom dess direkta värde är svårare att se och räkna. En fallstudie genomfördes för att definiera vilka typer av icke-värdeskapande aktiviteter som kan identifieras inom informationsflöden och för att avgöra om decentraliserad applikationsutveckling kan eliminera detta digitala slöseri. Ett internt informationsflöde modellerades, analyserades och optimerades genom att utveckla anpassade applikationer på Microsoft Power Platform. Baserat på litteratur från tillverknings- och mjukvaruutvecklingsområdet utvecklades en ram för att kategorisera digitalt slöseri samt högre grundorsaker när det gäller affärsstrategi och ITinfrastruktur. Medan decentraliserad apputveckling ger möjlighet att avsevärt minska det operativa digitala slöseriet på ett förenklat sätt, så kan det också möjliggöra onödig expansion av en gemensam datamodell och kräver hantering av livscykelanalyser samt kantsäkerhet för att säkerställa datahantering och styrning. Trots begränsad till en fallstudie, så kan det föreslagna ramverket ge insikter till organisationer som syftar till att optimera interna arbetsflöden genom att identifiera och eliminera digitalt slöseri och dess grundläggande orsaker.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Today’s flight test processing systems must handle many more complex data formats than just the PCM and analog FM data streams of yesterday. Many flight test programs, and their respective test facilities, are looking to leverage their computing assets across multiple customers and programs. Typically, these complex programs require the ability to handle video, packet, and avionics bus data in real time, in addition to handling the more traditional PCM format. Current and future telemetry processing systems must have an architecture that will support the acquisition and processing of these varied data streams. This paper describes various architectural designs of both staged data flow and stream computing architectures, including current and future implementations. Processor types, bus design, and the effects of varying data types, including PCM, video, and packet telemetry, will be discussed.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / The difficulty of incorporating custom real-time processing into a conventional telemetry system frustrates many design engineers. Custom algorithms such as data compression/conversion, software decommutation, signal processing or sensitive defense related algorithms, are often executed on expensive and time-consuming mainframe computers during post-processing. The cost to implement such algorithms on real-time hardware is greater, because programming for such hardware is usually done in assembly language or microcode, resulting in: * The need for specially trained software specialists * Long and often unpredictable development time * Poor maintainability * Non-portability to new applications or hardware. This paper presents an alternative to host-based, post-processing telemetry systems. The Loral System 500 offers an easy to use, high-level language programming environment that couples real-time performance with fast development time, portability and easy maintenance. Targeted to Weltek's XL-Serles 32 and 64 bit floating point processors, delivering 20 MFLOPS peak performance, the environment transparently integrates the C programming environment with a parallel date-flow telemetry processing architecture. Supporting automatic human interface generation, symbolic high-level debugging and a complete floating point math library the System 500 programming environment extends to parallel execution transparently. It handles process scheduling, memory management and data conversion automatically. Configured to run under UNIX, the system's development environment is powerful and portable. The platform can be migrated to PC's and other hosts, facilitating eventual integration with an array of standard off-the-shelf tools.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / The difficulty of incorporating custom real-time processing into a conventional telemetry system frustrates many design engineers. Custom algorithms such as data compression/conversion, software decommutation, signal processing or sensitive defense related algorithms, are often executed on expensive and timeconsuming mainframe computers during post-processing. The cost to implement such algorithms on real-time hardware is greater, because programming for such hardware is usually done in assembly language or microcode, resulting in: The need for specially trained software specialists Long and often unpredictable development time Poor maintainability Non-portability to new applications or hardware This paper presents an alternative to host-based, post-processing telemetry systems. The Loral System 500 offers an easy to use, high-level language programming environment that couples real-time performance with fast development time, portability and easy maintenance. Targeted to Weltek’s XL-Serles 32 and 64 bit floating point processors, delivering 20 MFLOPS peak performance, the environment transparently integrates the C programming environment with a parallel date-flow telemetry processing architecture. Supporting automatic human interface generation, symbolic high-level debugging and a complete floating point math library the System 500 programming environment extends to parallel execution transparently. It handles process scheduling, memory management and data conversion automatically. Configured to run under UNIX, the system’s development environment is powerful and portable. The platform can be migrated to PC’s and other hosts, facilitating eventual integration with an array of standard off-the-shelf tools.

Frappée par les rendements décroissants de la performance séquentielle et les limitations thermiques, l’industrie des microprocesseurs s’est tournée résolument vers les multiprocesseurs sur puce. Ce mouvement a ramené des problèmes anciens et difficiles sous les feux de l’actualité du développement logiciel. Les compilateurs sont l’une des pièces maitresses du puzzle permettant de poursuivre la traduction de la loi de Moore en gains de performances effectifs, gains inaccessibles sans exploiter le parallélisme de threads. Pourtant, la recherche sur les systèmes parallèles s’est concentrée sur les aspects langage et architecture, et le potentiel reste énorme en termes de compilation de programmes parallèles, d’optimisation et d’adaptation de programmes parallèles pour exploiter efficacement le matériel. Cette thèse relève ces défis en présentant Erbium, un langage de bas niveau fondé sur le traitement de flots de données, et mettant en œuvre des communications multi-producteur multi-consommateur ; un exécutif parallèle très efficace pour les architectures x86 et des variantes pour d’autres types d’architectures ; un schéma d’intégration du langage dans un compilateur illustré en tant que représentation intermédiaire dans GCC ; une étude des primitives du langage et de leurs dépendances permettant aux compilateurs d’optimiser des programmes Erbium à l’aide de transformations spécifiques aux programmes parallèles, et également à travers des formes généralisées d’optimisations classiques, telles que l’élimination de redondances partielles et l’élimination de code mort. / As transistors size and power limitations stroke computer industry, hardware parallelism arose as the solution, bringing old forgotten problems back into equation to solve the existing limitations of current parallel technologies. Compilers regain focus by being the most relevant puzzle piece in the quest for the expected computer performance improvements predicted by Moores law no longer possible without parallelism. Parallel research is mainly focused in either the language or architectural aspects, not really giving the needed attention to compiler problems, being the reason for the weak compiler support by many parallel languages or architectures, not allowing to exploit performance to the best. This thesis addresses these problems by presenting: Erbium, a low level streaming data-flow language supporting multiple producer and consumer task communication; a very efficient runtime implementation for x86 architectures also addressing other types of architectures; a compiler integration of the language as an intermediate representation in GCC; a study of the language primitives dependencies, allowing compilers to further optimise the Erbium code not only through specific parallel optimisations but also through traditional compiler optimisations, such as partial redundancy elimination and dead code elimination.