As the level of integrated circuit (IC) complexity continues to increase, the post-silicon validation stage is becoming a large component of the overall development cost. To address this, we propose a reconfigurable post-silicon debug infrastructure that enhances the post-silicon validation process by enabling the observation and control of signals that are internal to the manufactured device. The infrastructure is composed of dedicated programmable logic and programmable access networks. Our reconfigurable infrastructure enables not only the diagnoses of bugs; it also allows the detection and potential correction of errors in normal operation. In this thesis we describe the architecture, implementation and operation of our new infrastructure. Furthermore, we identify and address three key challenges arising from the implementation of this infrastructure. Our results demonstrate that it is possible to implement an effective reconfigurable post-silicon infrastructure that is able to observe and control circuits operating at full speed, with an area overhead of between 5% and 10% for many of our target ICs.

In the recent year, System-on-Chip (SoC) has become a popular and important issue. As the environment of the SoC design becomes more and more complex. The issue of system verification becomes more important. In previous, the intellectual property (IP) was developed dependently. Every designer just designed the IP without integrated with others. But with the complexity of the environment increasing, more and more IPs are integrated into a system. Even though the verification plans are more complex, but some protocol errors can also not found by designers. Some incautious behavior may cause the system deadlock or in a jam. Some research use protocol checker to verify bus protocol, but they can¡¦t synthesize, so we propose a rule-based and synthesizable style protocol checker(AXIChecker) to verify the transactions on the AXI bus conform the AMBA 3.0(AXI) protocol or not.

Tracing represents that the information which are generated from the system can be collected for later observation and analysis. Because the SoC design becomes more and more complex, an advanced tracing is needed instead of processor tracing only. However, the generation rate and the size of real time system traces are so huge such that the compressor for tracing is needed. In this thesis, we purpose an on-chip bus trace analyzer for SoC¡¦s. This trace analyzer can allowed to perform accurate, successive trace collection in an unlimited time and can be used in various embedded system without influencing the operation of the bus system. The approach consists of two stages: (1) timing/signal abstraction stage and (2) trace reducing stage. And we show how to design and implement the on-chip bus trace analyzer. It can be also configured by users for different debugging uses. The experimental results show that this bus trace analyzer can reach a good compression ratio of 99% for AMBA system. Hence, by utilizing this trace analyzer, the support for debugging can be more powerful than existing method.

In the System on a Chip () era, more components are embedded in one chip. Therefore, it has been an important issue to assist verification and debugging by observing the signals inside of a chip. The bus signals tracing is a general method to resolve it. However, the quantities of signals that have to be traced in an are very huge, we must to reduce the trace data as more as possible. Because of the reasons described as above, we propose a hardware called multi-resolution bus tracer to overcome these problems in this thesis. In the bus tracer, user can changes the observed accuracy of tracing signals dynamically during the program execution, and reduces all those signals efficiently. The experiment results show that bus tracer can achieve 85% average compressed ratio on the forward tracing, and 84% average compressed ratio on the backward tracing. In the other hand, the software called trace data analyzer not only transfers the trace signals into Value Change Dump (VCD) file format but also provides some essential analyses for user observation. Finally, our IP (Intelligent Property) has been integrated into a real platform: 3D Graphics Acceleration, and tape-out successfully. Therefore, using the multi-resolution bus trace analyzer can promote the abilities of system debugging efficiently.

As the level of integrated circuit (IC) complexity continues to increase, the post-silicon validation stage is becoming a large component of the overall development cost. To address this, we propose a reconfigurable post-silicon debug infrastructure that enhances the post-silicon validation process by enabling the observation and control of signals that are internal to the manufactured device. The infrastructure is composed of dedicated programmable logic and programmable access networks. Our reconfigurable infrastructure enables not only the diagnoses of bugs; it also allows the detection and potential correction of errors in normal operation. In this thesis we describe the architecture, implementation and operation of our new infrastructure. Furthermore, we identify and address three key challenges arising from the implementation of this infrastructure. Our results demonstrate that it is possible to implement an effective reconfigurable post-silicon infrastructure that is able to observe and control circuits operating at full speed, with an area overhead of between 5% and 10% for many of our target ICs.

As the level of integrated circuit (IC) complexity continues to increase, the post-silicon validation stage is becoming a large component of the overall development cost. To address this, we propose a reconfigurable post-silicon debug infrastructure that enhances the post-silicon validation process by enabling the observation and control of signals that are internal to the manufactured device. The infrastructure is composed of dedicated programmable logic and programmable access networks. Our reconfigurable infrastructure enables not only the diagnoses of bugs; it also allows the detection and potential correction of errors in normal operation. In this thesis we describe the architecture, implementation and operation of our new infrastructure. Furthermore, we identify and address three key challenges arising from the implementation of this infrastructure. Our results demonstrate that it is possible to implement an effective reconfigurable post-silicon infrastructure that is able to observe and control circuits operating at full speed, with an area overhead of between 5% and 10% for many of our target ICs. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

With the growing size of modern integrated circuit designs, automated design tools have taken an important role in the development flow. Through the use of these tools, designers can develop circuits in a robust and systematic manner. However, due to the high complexity of the designs and strict resource constraints, it is inevitable that mistakes will be made during the design process. Today, a significant amount of development time is dedicated to pre- and post-silicon verification and debug, which can increase the production cost and jeopardize the future growth of the industry. Hence, there is an urgent need for scalable automated verification and debugging techniques, as well as new methodologies that improve circuits in order to reduce errors. This dissertation presents a set of methodologies to automate three important processes in the VLSI design flow that are related to improving the quality of designs. The first contribution, automated logic restructuring, is a systematic methodology used to devise transformations in logic designs. This technique can be used for a wide range of post-synthesis applications, such as logic optimization, debugging and engineer change orders, which modify synthesized designs to accommodate their goals. Better results can be achieved if there are various transformations for those applications to select. Experiments demonstrate that the proposed technique is capable of re-structuring designs at a location where other methods fail and also identifies multiple transformations for each location. The second contribution is a logic-level, technology-independent soft error rate mitigation technique. Soft errors are transient logic pulses induced by radiation from the environment or released from the silicon chip package materials. This technique identifies conditions where soft errors can cause discrepancies at the primary outputs of the design, and eliminates those conditions through wire replacement. Experimental results confirm the effectiveness of the proposed technique and show that the soft error rate can be reduced at no or small additional overhead to other design parameters. The final contribution of the dissertation is a software environment for post-silicon debug. The proposed algorithms analyze the data collected during operating silicon chips at speed in the test system and provide useful information to expedite the debugging process. Experiments show that the proposed techniques eliminate one third of design modules, which are suspected as the root cause of the failure. Such a reduction can save engineers time on manual inspection and shorten the turnaround time of silicon debug.

With the growing size of modern integrated circuit designs, automated design tools have taken an important role in the development flow. Through the use of these tools, designers can develop circuits in a robust and systematic manner. However, due to the high complexity of the designs and strict resource constraints, it is inevitable that mistakes will be made during the design process. Today, a significant amount of development time is dedicated to pre- and post-silicon verification and debug, which can increase the production cost and jeopardize the future growth of the industry. Hence, there is an urgent need for scalable automated verification and debugging techniques, as well as new methodologies that improve circuits in order to reduce errors. This dissertation presents a set of methodologies to automate three important processes in the VLSI design flow that are related to improving the quality of designs. The first contribution, automated logic restructuring, is a systematic methodology used to devise transformations in logic designs. This technique can be used for a wide range of post-synthesis applications, such as logic optimization, debugging and engineer change orders, which modify synthesized designs to accommodate their goals. Better results can be achieved if there are various transformations for those applications to select. Experiments demonstrate that the proposed technique is capable of re-structuring designs at a location where other methods fail and also identifies multiple transformations for each location. The second contribution is a logic-level, technology-independent soft error rate mitigation technique. Soft errors are transient logic pulses induced by radiation from the environment or released from the silicon chip package materials. This technique identifies conditions where soft errors can cause discrepancies at the primary outputs of the design, and eliminates those conditions through wire replacement. Experimental results confirm the effectiveness of the proposed technique and show that the soft error rate can be reduced at no or small additional overhead to other design parameters. The final contribution of the dissertation is a software environment for post-silicon debug. The proposed algorithms analyze the data collected during operating silicon chips at speed in the test system and provide useful information to expedite the debugging process. Experiments show that the proposed techniques eliminate one third of design modules, which are suspected as the root cause of the failure. Such a reduction can save engineers time on manual inspection and shorten the turnaround time of silicon debug.

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use of the pins on the JTAG port. The development of system-on-chip technology has matured significantly in recent years. The microprocessors in system-on-chip designs have been applied in a variety of ways, and different microprocessors are being used in the embedded system. The traditional modus operandi of debug control, in which an ad hoc hardware/software package is required for each microprocessor, is not economical as far as programming and designing are concerned. Thus it is advisable to design a more flexible debug control hardware/software package which can fit into different embedded microprocessors with in-circuit emulators. This thesis reviews several types of embedded in-circuit emulator structure and comes up with a parameterized, modularized hardware/software package for controlling in-circuit emulators. An initial analysis of microprocessor systems and embedded debug circuits helps us to elicit reusable parameters so that we can achieve our desired debug control by simply adjusting parameters when we work on different microprocessor architectures and embedded debug circuits. An ensuing examination of the reusability and functionality of our designed debug control hardware/software enables us to group all the functions of our hardware/software package into different functional modules so that we can simply replace relevant functional modules on different microprocessor architectures and embedded debug circuits. The parameterized design allows us to use a single debug control software program on different microprocessor systems with the slightest change of parameter setting. The modularized model has the merit of minimizing our effort of debug control through module replacement when we need to adapt our software to a new environment (as when we want to use it on a different operating system or when we want to apply it to a different communication interface).

This thesis considers how to teach novices to debug computer programs. The investigation is specifically aimed at students in first year of computer science at university. The goal is to find an effective method of improving the debugging ability of novice subjects. Novices are less effective than experts. Although weaker across the board, novices display a critical lack of strategic skills in the debugging domain. Novices become lost and discouraged easily. Novices do not make good use of program structure, do not use test cases intelligently, and do not track their progress. Even a slight improvement in these aspects has the potential to significantly improve performance. Expert debugging behaviour was examined. This provided the basis for a model of debugging to be used in instructing novices. Teaching materials were developed to instruct and support students in following the model. The model and training were then tested in both laboratory and classroom situations. Results were mixed, with a generally positive trend. The model by itself was not overly effective. When the model was accompanied by training materials containing examples and scaffolding, students who were willing to spend time examining the training usually showed some improvement. In a few cases, the student's debugging style was dramatically improved. The improved performance seems to come partially from improved skill and partially from motivation. The model and materials show potential, and are likely to be more effective when used in an environment that allows interaction, rather than the current paper-based, non-interactive tutorial.