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This dissertation highlights that existing performance diagnostic tools often become less effective due to their inherent inaccuracies in modern software. To overcome these inaccuracies and effectively identify the root causes of performance issues, it is necessary to incorporate supplementary runtime information into these tools. Within this context, the dissertation integrates specific runtime information into two typical performance diagnostic tools: profilers and causal tracing tools. The integration yields a substantial enhancement in the effectiveness of performance diagnosis. Among these tools, gprof stands out as a representative profiler for performance diagnosis. Nonetheless, its effectiveness diminishes as the time cost calculated based on CPU sampling fails to accurately and adequately pinpoint the root causes of performance issues in complex software. To tackle this challenge, the dissertation introduces an innovative methodology called value-assisted cost profiling (vProf). This approach incorporates variable values observed during runtime into the profiling process. By continuously sampling variable values from both normal and problematic executions, vProf refines function cost estimates, identifies anomalies in value distributions, and highlights potentially problematic code areas that could be the actual sources of performance is- sues. The effectiveness of vProf is validated through the diagnosis of 18 real-world performance is- sues in four widely-used applications. Remarkably, vProf outperforms other state-of-the-art tools, successfully diagnosing all issues, including three that had remained unresolved for over four years. Causal tracing tools reveal the root causes of performance issues in complex software by generating tracing graphs. However, these graphs often suffer from inherent inaccuracies, characterized by superfluous (over-connected) and missed (under-connected) edges. These inaccuracies arise from the diversity of programming paradigms. To mitigate the inaccuracies, the dissertation proposes an approach to derive strong and weak edges in tracing graphs based on the vertices’ semantics collected during runtime. By leveraging these edge types, a beam-search-based diagnostic algorithm is employed to identify the most probable causal paths. Causal paths from normal and buggy executions are differentiated to provide key insights into the root causes of performance issues. To validate this approach, a causal tracing tool named Argus is developed and tested across multiple versions of macOS. It is evaluated on 12 well-known spinning pinwheel issues in popular macOS applications. Notably, Argus successfully diagnoses the root causes of all identified issues, including 10 issues that had remained unresolved for several years. The results from both tools exemplify a substantial enhancement of performance diagnostic tools achieved by harnessing runtime information. The integration can effectively mitigate inherent inaccuracies, lend support to inaccuracy-tolerant diagnostic algorithms, and provide key insights to pinpoint the root causes.

PLCs are extensively used for the discrete and continuous control of non-intelligent shop-floor devices. The debugging phase of ladder logic development for PLCs is very cumbersome and difficult. Most often on-line debugging which is expensive and time consuming is used for debugging. Computer simulation techniques applied to this problem, leaves much to be desired. The best technique developed for ladder logic debugging is the use of ladder-based triggers. A ladder-based trigger is a function which suspends simulation execution whenever a vector of ladder variables equates to a vector of predefined states. System-based debugging facilities are those which aid a programmer in error detection at the system level. System based triggers will identify system faults and set traps within a simulation model to detect their occurrence. This approach will provide information necessary for a faster correction of the ladder logic once a trigger is activated. The system based debugging tool developed is capable of scanning a boolean representation of a PLC program with input coils, counters, timers, "and" conditions, "or conditions and output coils. The program provides the following facilities: 1. Graphics programs can be attached to the simulation program for better visualization. 2. The simulation program allows interactive control over the test bed developed. In a non-interactive simulation it can be executed in a timed sequential mode or random mode. 3. Triggers can be set by the user depending on the conditions that are to be monitored. 4. The program stops execution whenever a trigger is activated. 5. The program provides a trace of the output that caused the trigger and also of the inputs to this output, along with their state values at the time of activation. The use of system based techniques and graphics in the debugging of PLC ladder logic is demonstrated. Further the use of an object oriented frame work in the development of the debugging software is also demonstrated. / Master of Science

A simulator for use in programmable controller ladder logic testing is developed. A simulation language, based on SIMSCRIPT 11.5, to model ladder logic run physical systems is also designed. This System Description Language (SDL) handles simulations of the physical systems and the corresponding ladder-system interactions via the usage of specially designed constructs. The simulation package uses as input an SDL program file describing the system to be simulated, and a ladder file containing the ladder written to control this system. The simulation processor generates the actual simulation from the description contained in the SDL program file. A ladder scanning procedure approximates the actual programmable controller scan as closely as possible. The simulator also incorporates the ability for the user to dynamically interact with, and control the simulation by manipulating ladder inputs from the keyboard. A rolling timing diagram display of a maximum of 7 elements can be created and continuously updated for viewing purposes. System simulations of functionally different manufacturing systems are created and run with their respective ladders on the simulator. Different ladders for the same system are compared for evaluating the performance of the control logic of each ladder. These comparisons are based on the viewing of timing diagrams generated by the ladders. Thus, an off-line ladder logic debugging environment is created. / Master of Science

Execution history (EH) analysis is a major unexplored area in the development of debugging technology. In this dissertation we develop a theoretical foundation for incorporating EH analysis into the process of automatically debugging programs written in imperative, strongly typed, procedure oriented languages. This foundation includes the construction of a model for EH representation, an analysis of run time errors within the model, and the development of an approach to the use of EH analysis in automatic debugging. The model represents an execution history as a sequence of state vectors. Each vector contains both the values of program variables at a particular point in a computation and additional information that is used in the debugging process. Within this model, run time errors are classified by their effect on program termination, and characterized by their appearance within the EH. Based on this classification and characterization, techniques for detecting errors within an EH are presented. These techniques form the basis of an approach to automatic debugging in which a deterministic analysis locates errors in the execution history and, based on the results of this search, heuristic techniques perform automatic fault Localization. / Ph. D.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1981 / Bibliography: leaves 59-60. / by Daniel Goodman Shapiro. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

The problems of software debugging and system reliability/availability are among the most challenging problems the computing industry is facing today, with direct impact on the development and operating costs of computing systems. A promising debugging technique that assists programmers identify and fix the causes of software bugs a lot more efficiently is bidirectional debugging, which enables the user to execute the program in "reverse", and a typical method used to recover a system after a fault is backwards error recovery, which restores the system to the last error-free state. Both reverse execution and backwards error recovery are enabled by creating memory checkpoints, which are used to restore the program/system to a prior point in time and re-execute until the point of interest. The checkpointing frequency is the primary factor that affects both the latency of reverse execution and the recovery time of the system; more frequent checkpoints reduce the necessary re-execution time. Frequent creation of checkpoints poses performance challenges, because of the increased number of memory reads and writes necessary for copying the modified system/program memory, and also because of software interventions, additional synchronization and I/O, etc., needed for creating a checkpoint. In this thesis I examine a number of different hardware accelerators, whose role is to create frequent memory checkpoints in the background, at minimal performance overheads. For the purpose of reverse execution, I propose the HARE and Euripus hardware checkpoint accelerators. HARE and Euripus create different types of checkpoints, and employ different methods for keeping track of the modified memory. As a result, HARE and Euripus have different hardware costs and provide different functionality which directly affects the latency of reverse execution. For improving the availability of the system, I propose the Kyma hardware accelerator. Kyma enables simultaneous creation of checkpoints at different frequencies, which allows the system to recover from multiple types of errors and tolerate variable error-detection latencies. The Kyma and Euripus hardware engines have similar architectures, but the functionality of the Kyma engine is optimized for further reducing the performance overheads and improving the reliability of the system. The functionality of the Kyma and Euripus engines can be combined into a unified accelerator that can serve the needs of both bidirectional debugging and system recovery.

by Lam, Hin-ki Isaac. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1992. / Includes bibliographical references (leaves 219-220). / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- The Problem --- p.1 / Chapter 1.2 --- Related Works --- p.3 / Chapter 1.3 --- Contribution of the Present Study --- p.8 / Chapter 1.4 --- Outline of the Thesis --- p.8 / Chapter Chapter 2 --- Nontermination and Recursive Definition --- p.11 / Chapter 2.1 --- Prolog Execution Model --- p.11 / Chapter 2.2 --- Nontermination --- p.15 / Chapter 2.3 --- Exit Condition --- p.21 / Chapter 2.4 --- Exit-Reaching Process --- p.29 / Chapter 2.5 --- Parameter Based Detection --- p.35 / Chapter Chapter 3 --- Parameter Analysis --- p.38 / Chapter 3.1 --- Parameter Links --- p.39 / Chapter 3.1.1 --- Parameter Links and Parameter Modifying Process --- p.39 / Chapter 3.1.2 --- Parameter Links of Multi-Parameters --- p.43 / Chapter 3.1.3 --- Parameter Links in Indirect Recursive Definition --- p.44 / Chapter 3.1.4 --- Parameter Links with Special Parameters --- p.46 / Chapter 3.1.5 --- Parameter Links of the Same Name Parameters --- p.47 / Chapter 3.1.6 --- The Significance of Parameter Links --- p.49 / Chapter 3.2 --- Cyclic Parameter Links --- p.51 / Chapter 3.3 --- Parameter Link Detection --- p.58 / Chapter 3.3.1 --- Graph Technique --- p.58 / Chapter 3.3.1.1 --- Preliminaries --- p.58 / Chapter 3.3.1.2 --- on Parameter Links --- p.59 / Chapter 3.3.2 --- Algorithms --- p.62 / Chapter Chapter 4 --- Data Analysis --- p.70 / Chapter 4.1 --- Data Links --- p.72 / Chapter 4.1.1 --- The Direct Recursive Definition Case --- p.76 / Chapter 4.1.1.1 --- Subgoal Procedures with Facts Alone --- p.76 / Chapter 4.1.1.2 --- Procedures with Rules --- p.79 / Chapter 4.1.2 --- The Indirect Recursive Definition Case --- p.84 / Chapter 4.2 --- on the Difference between Pure and General Prolog --- p.86 / Chapter 4.3 --- Data Link Significance --- p.89 / Chapter 4.4 --- Connected Data-link Lists --- p.92 / Chapter 4.4.1 --- Data Links and Connected Data-link Lists --- p.92 / Chapter 4.4.1.1 --- Connected Data-link Lists and Data Transfer Sequence --- p.95 / Chapter 4.4.1.2 --- Connected Data-link Lists and Backtracking --- p.97 / Chapter 4.4.1.3 --- Connected Data-link Lists and the Recursion Result --- p.99 / Chapter 4.4.2 --- Cyclic and Non-Cyclic Connected Data-link Lists --- p.100 / Chapter 4.4.2.1 --- Non-Cyclic Connected Data-link Lists and Exit Conditions --- p.102 / Chapter 4.4.2.2 --- Cyclic Connected Data-link Lists and Nontermination --- p.104 / Chapter 4.4.3 --- Multi-Connected Data-link Lists --- p.107 / Chapter 4.4.3.1 --- in One Cyclic Parameter Link --- p.107 / Chapter 4.4.3.2 --- in Multi-Cyclic Parameter Links --- p.115 / Chapter 4.4.3.3 --- The Case of Multiple Recursive Subgoals in the Same Rule --- p.120 / Chapter 4.5. --- Special Parameters and Data Links --- p.125 / Chapter 4.5.1. --- Data Links with Special Parameters Only --- p.126 / Chapter 4.5.2 --- Data Links with Both Special Parameters and Subgoals --- p.136 / Chapter 4.6 --- Data Links and Infinite Data Transfer Sequence Detection --- p.142 / Chapter CHAPTER 5 --- Special Cases --- p.150 / Chapter 5.1 --- Interdependent Cyclic Parameter Links --- p.150 / Chapter 5.1.1 --- Interdependent Cyclic Parameter Links through Common Parameters --- p.151 / Chapter 5.1.1.1 --- Interdependency between Cyclic and Non-cyclic Parameter Links and Interdependency between Cyclic Parameter Link and Subgoals --- p.158 / Chapter 5.1.1.2 --- Interdependency between Cyclic Parameter Links --- p.165 / Chapter 5.1.1.2.1 --- Lengths of Cyclic Connected- data Links in Different Ratios --- p.171 / Chapter 5.1.1.2.2 --- Cyclic Parameter Links with Lengths in Different Ratios --- p.182 / Chapter 5.1.2 --- Interdependent Cyclic Parameter Links through Common Subgoals --- p.196 / Chapter 5.1.3 --- Interdependent Cyclic Parameter Links with Special Parameters --- p.202 / Chapter 5.2 --- A Special Case of Cyclic Parameter Links established through Special Parameters --- p.208 / Chapter CHAPTER 6 --- Discussion and Conclusion --- p.213 / Chapter 6.1 --- The Results and Implications --- p.213 / Chapter 6.2 --- Limitations and Future Research --- p.215 / Chapter 6.3 --- Conclusion --- p.217 / Reference --- p.219

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 40-41. / by Michael Henry Bulat. / B.S.

This thesis describes TeaBag, which is a debugger for functional logic computations. TeaBag is an accessory of a virtual machine currently under development. A distinctive feature of this machine is its operational completeness of computations, which places novel demands on a debugger. This thesis describes the features of TeaBag, in particular the handling of non-determinism, the ability to control nondeterministic steps, to remove context information, to toggle eager evaluation, and to set breakpoints on both functions and terms. This thesis also describes TeaBag's architecture and its interaction with the associated virtual machine. Finally, some debugging sessions of defective programs are presented to demonstrate TeaBag's ability to locate bugs. A distinctive feature of TeaBag is how it presents non-deterministic trace steps of an expression evaluation trace to the user. In the past expression evaluation traces were linearized via backtracking. However, the presence of backtracking makes linear traces difficult to follow. TeaBag does not present backtracking to the user. Rather TeaBag presents the trace in two parts. One part is the search space which has a tree structure and the other part is a linear sequence of steps for one path through the search space.