Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 75-79). Also available in electronic format on the Internet.

Thesis (M.S.)--Ohio University, August, 1995. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, March, 2004. / Includes bibliographical references (p. 90-91).

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 109-110). Also available in electronic format on the Internet.

Thesis (M.S.)--Ohio University, March, 2004. / Title from PDF t.p. Includes bibliographical references (p. 90-91)

Thesis (Ph. D.)--University of Canterbury, 2007. / Typescript (photocopy). "June 2007." Includes bibliographical references (p. 159-166). Also available via the World Wide Web.

Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on hardware implementation of (3, 6) - regular LDPC codes. A fully parallel decoder will require too high complexity of hardware realization. Partly parallel decoder has the advantage of effective compromise between decoding throughput and high hardware complexity. The decoding of the codeword follows the belief propagation alias probability propagation algorithm in log domain. A 9216 bit, (3, 6) regular LDPC code with code rate ½ was implemented on FPGA targeting Xilinx Virtex 4 XC4VLX80 device with package FF1148. This decoder achieves a maximum throughput of 82 Mbps. The entire model was designed in VHDL in the Xilinx ISE 9.2 environment.

A Dissertation submitted in ful llment of the requirements for the degree of Master of Science in the School of Electrical and Information Engineering January, 2017 / Permutation codes provide the required redundancy for error correction in a noisy communication channel. Combined with MFSK modulation, the outcome produces an e cient system reliable in combating background and impulse noise in the com- munication channel. Part of this can be associated with how the redundancy scales up the amount of frequencies used in transmission. Permutation coding has also shown to be a good candidate for error correction in harsh channels such as the Powerline Communication channel. Extensive work has been done to construct permutation code books but existing decoding algorithms become impractical for large codebook sizes. This is because the algorithms need to compare the received codeword with all the codewords in the codebook used in encoding. This research therefore designs an e cient soft-decision decoder of Permutation codes. The decoder's decision mechanism does not require lookup comparison with all the codewords in the codebook. The code construction technique that derives the codebook is also irrelevant to the decoder. Results compare the decoding algorithm with Hard-decision plus Envelope Detec- tion in the Additive White Gaussian Noise (AWGN) and Rayleigh Fading Channels. The results show that with lesser iterations, improved error correction performance is achieved for high-rate codes. Lower rate codes require additional iterations for signi cant error correction performance. The decoder also requires much less comup- tational complexity compared with existing decoding algorithms. / MT2017

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 101-107). Also available in electronic format on the Internet.

A codificação de vídeo digital é um recurso essencial para a produção de vídeo para a Internet, canais de TV e outras mídias. Através da codificação é possível melhorar a utilização de recursos de armazenamento, transmissão e recepção, como por exemplo, banda. Em sistemas embarcados, a limitação de recursos impacta no desempenho dos codificadores, como por exemplo, as câmeras de vídeo de telefones celulares. Este trabalho analisa o uso de técnicas para a diminuição de acesso a memória externa (RAM) especificamente para o codificador x264. Através do uso de ferramentas para software profiling e análise da performance do codificador a partir dos contadores de performance (HPC) disponíveis em muitos processadores modernos, foi possível estabelecer um método de análise de dados para direcionar a implementação do codificador para um melhor desempenho. Os resultados obtidos mostram uma melhora entre 16% e 18% no tempo de codificação em relação a um codificador não otimizado, mantendo-se os mesmos valores de qualidade de vídeo obtidos através de métricas objetivas. / This study attempts to systematize the use of techniques to reduce access to external memory (RAM) for the x264 encoder, as well the use of software profiling tools with focus on the usage of hardware performance counters (HPC), available in many modern processors. The results show up a reduction between 16% and 18% for execution time of the encoder, without noticeable changes on objective video quality metrics. Digital video coding is an essential resource to produce video for Internet, TV, and other media. Through video coding, it is possible to improve storage and bandwidth utilization for transmission and reception of video streams. On embedded devices, hardware resources impact on the encoder performance, for example, in video cameras of cellphones. This study analyzes the external memory access (RAM) at the x264 encoder implementation, aiming to identify ways to improve the encoding process performance. With software profiling tools and encoder performance analysis was possible to establish a data analysis method which results can be used to improve the overall encoder performance. The method implementation results show an improvement of 16% to 18% over a non-optimized encoder while keeping the same video quality measured from objective metrics.