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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Measurements and Models of One-Way Transit Time in IP Routers / Mätningar av en-vägskorsningstid i IP routrar

Constantinescu, Doru January 2005 (has links)
The main goals of this thesis are towards an understanding of the delay process in best-effort Internet for both non-congested and congested networks. A novel measurement system is reported for delay measurements in IP routers, which follows specifications of the IETF RFC 2679. The system employs both passive measurements and active probing and offers the possibility to measure and analyze different delay components of a router, e.g., packet processing delay, packet transmission time and queueing delay at the output link. Dedicated application-layer software is used to generate UDP traffic with TCP-like characteristics. Pareto traffic models are used to generate self-similar traffic in the link. The reported results are in form of several important statistics regarding processing and queueing delays of a router, router delay for a single data flow, router delay for multiple data flows as well as end-to-end delay for a chain of routers. They confirm results reported earlier about the fact that the delay in IP routers is generally influenced by traffic characteristics, link conditions and, to some extent, details in hardware implementation and different IOS releases. The delay in IP routers may also occasionally show extreme values, which are due to improper functioning of the routers. Furthermore, new results have been obtained that indicate that the delay in IP routers shows heavy-tailed characteristics, which can be well modeled with the help of several distributions, either in the form of a single distribution or as a mixture of distributions. There are several components contributing to the OWTT in routers, i.e., processing delay, queueing delay and service time. The obtained results have shown that, e.g., the processing delay in a router can be well modeled with the Normal distribution, and the queueing delay is well modeled with a mixture of Normal distribution for the body probability mass and Weibull distribution for the tail probability mass. Furthermore, OWTT has several component delays and it has been observed that the component delay distribution that is most dominant and heavy-tailed has a decisive influence on OWTT. / Mätningar och modeller för en-vägskorsningstid presenteras.
2

Process Variability-Aware Performance Modeling In 65 nm CMOS

Harish, B P 12 1900 (has links)
With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
3

Mobile Ad Hoc Molecular Nanonetworks

Guney, Aydin 01 June 2010 (has links) (PDF)
Recent developments in nanotechnology have enabled the fabrication of nanomachines with very limited sensing, computation, communication, and action capabilities. The network of communicating nanomachines is envisaged as nanonetworks that are designed to accomplish complex tasks such as drug delivery and health monitoring. For the realization of future nanonetworks, it is essential to develop novel and efficient communication and networking paradigms. In this thesis, the first step towards designing a mobile ad hoc molecular nanonetwork (MAMNET) with electrochemical communication is taken. MAMNET consists of mobile nanomachines and infostations that share nanoscale information using electrochemical communication whenever they have a physical contact with each other. In MAMNET, the intermittent connectivity introduced by the mobility of nanomachines and infostations is a critical issue to be addressed. In this thesis, an analytical framework that incorporates the effect of mobility into the performance of electrochemical communication among nanomachines is presented. Using the analytical model, numerical analysis for the performance evaluation of MAMNET is obtained. Results reveal that MAMNET achieves adequately high throughput performance to enable frontier nanonetwork applications with sufficiently low communication delay.
4

Optimistic Coarse-Grained Cache Semantics for Data Marts

Lehner, Wolfgang, Thiele, Maik, Albrecht, Jens 15 June 2022 (has links)
Data marts and caching are two closely related concepts in the domain of multi-dimensional data. Both store pre-computed data to provide fast response times for complex OLAP queries, and for both it must be guaranteed that every query can be completely processed. However, they differ extremely in their update behaviour which we utilise to build a specific data mart extended by cache semantics. In this paper, we introduce a novel cache exploitation concept for data marts - coarse-grained caching - in which the containedness check for a multi-dimensional query is done through the comparison of the expected and the actual cardinalities. Therefore, we subdivide the multi-dimensional data into coarse partitions, the so called cubletets, which allow to specify the completeness criteria for incoming queries. We show that during query processing, the completeness check is done with no additional costs.

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