Ho, Yee Man Martina = 硒化鎘三維納米結構之製作及其感應脫氧核糖核酸之應用潛能 / 何綺雯. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Ho, Yee Man Martina = Xi hua ge san wei na mi jie gou zhi zhi zuo ji qi gan ying tuo yang he tang he suan zhi ying yong qian neng / He Qiwen. / Chapter Chapter 1 --- Introduction / Chapter 1 --- Photovoltaic properties of CdSe --- p.1 / Chapter 1.1 --- Quantum size effect --- p.1 / Chapter 1.2 --- Synthesis of CdSe nanostructures --- p.3 / Chapter 1.3 --- Electrochemical sensing of CdSe nanostructures --- p.4 / Chapter 1.3.1 --- Surface passivation and functionalization of CdSe nanostructures --- p.5 / Chapter 1.4 --- Electronic properties of nanocrystalline semiconductor electrode --- p.6 / Chapter 1.4.1 --- Band alignment --- p.6 / Chapter 1.4.2 --- Interfacial charge transfer process --- p.9 / Chapter 1.4.3 --- Surface traps and adsorbed molecules --- p.10 / Chapter 1.4.4 --- DNA molecules as a capping group --- p.11 / Chapter 1.5 --- Literatures review in DNA sensing --- p.12 / Chapter 1.6 --- Present study --- p.14 / Chapter 1.6.1 --- Objective --- p.14 / Chapter 1.6.2 --- General methodology --- p.15 / Chapter Chapter 2 --- Experimental / Chapter 2.1 --- Introduction into the instrumentation of this project --- p.21 / Chapter 2.2 --- CHI Electrochemical workstation --- p.22 / Chapter 2.2.1 --- Linear sweep voltammetry --- p.24 / Chapter 2.2.2 --- Cyclic voltammetry --- p.24 / Chapter 2.2.3 --- Multiple potential step --- p.25 / Chapter 2.3 --- CEM Microwave-assisted chemical synthesizer --- p.27 / Chapter 3.1 --- Morphological examination by scanning electron microscopy --- p.28 / Chapter 3.2 --- Elemental analysis by energy dispersive x-ray spectroscopy --- p.30 / Chapter 3.3 --- Crystal structure analysis by x-ray diffraction --- p.31 / Chapter 3.4 --- Surface compositional analysis by x-ray photoelectron spectroscopy --- p.32 / Chapter 3.5 --- Transmission electron microscopy --- p.34 / Chapter Chapter 3 --- Synthesis of 3D nanostructured CdSe multipod electrodes / Chapter 3.1 --- Introduction into the synthesis of CdSe MP electrode --- p.35 / Chapter 3.2 --- Recipe for the synthesis of CdSe NPs --- p.36 / Chapter 3.3 --- The synthesis of CdSe MPs --- p.37 / Chapter 3.3.1 --- Tuning the experimental parameters: Reaction temperature --- p.37 / Chapter 3.3.2 --- Tuning the experimental parameters: Reaction hold time --- p.46 / Chapter 3.3.3 --- Tuning in experimental parameters: Precursor molar ratio --- p.50 / Chapter 3.4 --- The fabrication of MP CdSe on a conductive substrate --- p.54 / Chapter 3.4.1 --- The electrodeposition of CdSe thin films on ITO/glass substrates --- p.55 / Chapter 3.4.2 --- The growth of CdSe MPs on CdSe/ ITO/glass --- p.57 / Chapter 3.5 --- The characterization of MP CdSe electrode --- p.57 / Chapter Chapter 4 --- Electrical and opto-electric characteristics of CdSe MP electrodes and their applications as platforms for the DNA recognition / Chapter 4.1 --- Introduction to the property characterization of CdSe MP electrodes --- p.62 / Chapter 4.2 --- DNA surface attachment --- p.64 / Chapter 4.2.1 --- Mechanism of DNA surface anchoring --- p.65 / Chapter 4.3 --- I-V characterization in PBS --- p.69 / Chapter 4.3.1 --- Experimental procedures of the I-V tests in PBS --- p.70 / Chapter 4.3.2 --- Results and discussions of I-V tests in PBS --- p.72 / Chapter 4.3.2.1 --- Exercising as-prepared CdSe MP electrode --- p.74 / Chapter 4.3.2.2 --- I-V characteristics of CdSe MP electrodes before and after ssDNA attachment --- p.75 / Chapter 4.3.2.3 --- I-V characteristics of CdSe MP electrodes before and after the dsDNA attachment --- p.76 / Chapter 4.3.2.4 --- "Photo-response of bare CdSe MP, ssDNA/CdSe MP and dsDNA/CdSe electrodes" --- p.77 / Chapter 4.4 --- "Photovoltaic I-V measurement in I3""/I"" redox electrolyte" --- p.79 / Chapter 4.4.1 --- Experimental procedures --- p.79 / Chapter 4.4.2 --- Results and discussions --- p.80 / Chapter 4.5 --- Possible application implied by the results --- p.88 / Chapter 4.5.1 --- DNA base pair mismatch identification --- p.91 / Chapter 4.5.2 --- Field-assisted DNA hybridization acceleration process --- p.92 / Chapter Chapter 5 --- Conclusions / Chapter 5.1 --- Conclusions --- p.95

Jiang, Mingqi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves [49]-51). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- REWIRE --- p.6 / Chapter 2.2 --- GBAW --- p.7 / Chapter 3 --- Retiming --- p.9 / Chapter 3.1 --- Min-Clock Period Retiming --- p.9 / Chapter 3.2 --- Min-Area Retiming --- p.17 / Chapter 3.3 --- Retiming for Low Power --- p.18 / Chapter 3.4 --- Retiming with Interconnect Delay --- p.22 / Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26 / Chapter 4.1 --- Motivation and Problem Formulation --- p.26 / Chapter 4.2 --- Retiming Indication --- p.29 / Chapter 4.3 --- Target Wire Selection --- p.31 / Chapter 4.4 --- Incremental Placement Update --- p.33 / Chapter 4.5 --- Optimization Flow --- p.36 / Chapter 4.6 --- Experimental Results --- p.38 / Chapter 5 --- Power Analysis for Rewired Retiming --- p.41 / Chapter 5.1 --- Power Model --- p.41 / Chapter 5.2 --- Experimental Results --- p.44 / Chapter 6 --- Conclusion --- p.47 / Bibliography --- p.50

Includes bibliographical references (leaves 272-279.)

Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block of these circuits. This thesis studies gain stages that eliminate the internal compensation, thus allowing the SC circuits to operate at significantly higher operating speeds. An inverter-based SC integrator is presented. The proposed SC integrator is built with a pseudo-differential structure to improve its rejection of common-mode noise, such as charge injection and clock feedthrough. The proposed integrator also incorporates correlated double sampling (CDS) to boost its effective DC gain. Clock-boosting and switch bootstrapping techniques are not used in the proposed circuit, even though it uses a low supply voltage. To verify the speed advantage of the proposed circuit, a high speed delta sigma (Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation and layout floorplan are described. The design is based on MATLAB and SpectreS simulations. / Graduation date: 2002

A considerable amount of research has focused on load-sharing and system effects in repetitive-member wood floor systems subject to transverse loading. However, relatively few studies have been conducted to investigate load-sharing and system effects in repetitive-member wall systems which may be subject to combined transverse and gravity (vertical) loading, and which may have different boundary conditions from floors. This research investigates load-sharing and system effects in light-frame wood wall systems and seeks to develop repetitive-member system factors for codified design that rationally account for load sharing and other system effects. These factors are intended for use in the design of individual wall members, much as repetitive-member factors are used in the design of parallel-member floor and roof systems. As part of this research, an analytical model was developed to account for partial composite action, two-way action, and openings in the wall system. The model was validated using experimental test results and was shown to be able to predict reasonably well the response of light-frame wall systems. The model was then incorporated into a Monte Carlo simulation to perform reliability analyses of light-frame wall systems. Since the structural model is complex, and including a time-history analysis within the time-dependent simulation was not computationally practical, the load combination issue was considered separately from the reliability analysis. Sensitivity studies were conducted to investigate how different system parameters affect strength and reliability of light-frame wall systems. The reliability of light-frame wall systems was next evaluated using a portfolio of representative light-frame wall systems designed according to current code provisions. This portfolio approach was also used in evaluating system factors for light-frame wall systems. Thus, two different approaches (a reliability-based approach and a strength-ratio approach) were considered for developing system factors for member-design to account for load sharing, partial composite action and other system effects. Using the strength-ratio approach, a new framework for system factors (i.e., partial system factors) is suggested in which the effects of partial composite action, load sharing, load redistribution and system size (number of members) are treated separately. / Graduation date: 2003

The determination of the optimal location of transceivers is a critical design factor when deploying a wireless local area network (WLAN). The performance of the WLAN will improve in a variety of aspects when the transceivers' locations are adequately determined, including the overall cell coverage to the battery life of the client units. Currently, the most common method to determine the appropriate location of transceivers is known as a site survey, which is normally a very time and energy consuming process. The main objective of this research was to improve current methodologies for the optimal or near-optimal placement of APs in a WLAN installation. To achieve this objective, several improvements and additions were made to an existing computational tool to reflect the evolution that WLAN equipment has experienced in recent years. Major additions to the computational tool included the addition of the capability to handle multiple power levels for the transceivers, the implementation of a more adequate and precise representation of the passive interference sources for the path loss calculations, and the definition of a termination criterion to achieve reasonable computational times without compromising the quality of the solution. An experiment was designed to assess how the improvements made to the computational tool provided the desired balance between computational time and the quality of the solutions obtained. The controlled factors were the level of strictness of the termination criterion (i.e., high or low), and the number of runs performed (i.e., 1, 5, 10, 15, and 20 runs). The low level of strictness proved to dramatically reduce (i.e., from 65 to 70%) the running time required to obtain an acceptable solution when compared to that obtained at the high level of strictness. The quality of the solutions found with a single run was considerably lower than that obtained with the any other number of runs. On the other hand, the quality of the solutions seemed to stabilize at and after 10 runs, indicating that there is no added value to the quality of the solution when 15 or 20 runs are performed. In summary, having the computational tool developed in this research execute 5 runs with the low level of strictness would generate high quality solutions in a reasonable running time. / Graduation date: 2004

More than 1.2 million people worldwide require regular hemodialysis therapy to treat end stage renal failure. In the United States alone, there are 300,000 patients and the National Kidney Foundation predicts that this number will double in the next 10 years. Currently most dialysis patients receive treatment at a dialysis center and need three 4-5 hour treatments each week. While these treatments are useful, more frequent and longer duration dialysis better simulates natural kidney function. Consequently, at-home hemodialysis is expected to provide patients a better quality of life. Current hemodialysis systems are too expensive to support at-home hemodialysis. Cost drivers include the capital costs of the hemodialysis equipment and the raw material costs of expensive hemodialysis membranes. Microchannel hemodialysers have smaller form factors requiring significantly less membrane while enabling reductions in the size and cost of capital equipment. Microchannel devices are typically made by microchannel lamination methods involving the patterning, registration and bonding of thin laminae. Findings in this paper show that membrane utilization is highly dependent on registration accuracy with membrane utilization often dropping below 25%. Efforts here focus on the development of a self-registration method for assembling microchannel hemodialysers capable of supporting registration accuracies below 25 ��m over a 50 mm polycarbonate lamina. Using these methods, registration accuracies below 13 ��m were measured over a 50 mm scale. A mass transfer test article was produced with measured average one dimensional misregistration below 19 ��m with a demonstrated membrane utilization of 44.9% when considering both microchannel and header regions. Mass transfer results suggest that the device performed with a mass transfer area of 90.59 mm��. A design is proposed describing membrane utilization of over 79%. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from 9-17-2012 - 9-17-2013

Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero. A mixed-signal implementation has been chosen for the parallel MDFE, in which coefficients for the 9-tap feedback filter are adapted in the digital domain by 10-bit up/ down counters; 6-bit current mode D/A converters are used to convert digital coefficients to differential current signals which are summed with the forward equalizer (FE) output, and a flash A/D is used to make decisions and generate error signals for adaptation. In this thesis, a description of the parallel structure and the adaptation algorithm are presented with behavioral level verification. The circuit design and layout were carried out in HP 1.2um n-well CMOS process. The design of the high-speed counter and the current-mode D/A are discussed. HSPICE simulations show that a symbol rate of 100Mb/s for the feedback equalizer is readily achieved. / Graduation date: 1997

Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using digital FIR filters preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the major contributers to the power dissipation. However, this project focuses on the analog IC implementations of the DFE to achieve high speed and low power consumption. In other words, this project gets intensively involved in the design of a large-input highly-linear voltage-to-current converter, the design of a high-speed low-power 6-bit comparator, and the design of a high-speed low-power 6-bit current-steering D/A converter. The design and layout for the proposed analog equalizer are carried out in a 1.2 pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz clock frequency and 6-bit accuracy can be easily achieved. The power consumption for all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997

This work is concerned with the modeling and analysis of lossy planar dielectric optical waveguides. Loss mechanisms which affect propagation characteristics are reviewed, and various representations of the propagation constant in the lossy case are defined. Waveguide structures which are susceptable to absorption and/or to leakage loss, in particular silicon-based structures, are discussed. The modeling and analysis of these waveguides by various computational techniques is considered. Two computational methods, the commonly used transfer matrix method and the recently developed impedance boundary method of moments (IBMOM), are reviewed and extended to the complex domain. A third computational method, which offers improved convergence of the IBMOM for structures with large stepwise changes in refractive index, is formulated. In this approach, the regions containing refractive index discontinuities are replaced by equivalent extended impedance boundary conditions, and expansion of the transverse field in the remaining region of continuous refractive index profile is carried out. A significant increase in the rate of convergence is demonstrated for various waveguide structures, including an anti-resonant reflecting optical waveguide (ARROW) structure. Two applications of the IBMOM with extended impedance boundary conditions are presented. In the first, the method is applied to the design of a chemical sensor. The sensor, a silicon-based ARROW structure, is designed to measure the refractive index of certain chemical substances with a high degree of accuracy. In a second application, graded index SiON waveguides fabricated at Oregon State University are characterized and compared to the theoretical model. Excellent agreement between the theoretical and measured coupling angles is shown. / Graduation date: 1996