Denne oppgaven er stilt av Aptina Norway AS og tar for seg utviklingen av et FPGA-basert system for emulering av output fra en A/D-omformer i en CMOS-bildesensor.Dette systemet er ment a benyttes til verisering av RTL-design til CMOS-bildesensorprodukter. Emulatoren bruker en tilnrming til normalfordelingen for aemulere foton-, rad- og kolonnesty, og kan kjre pa frekvenser opp til 124:81 MHz.Dette gjr at emulatoren kan behandle 60 bilder i sekundet med full HD-opplsning. Systemet lar brukeren bestemme opplsning, stytyper og eventueltstandardavvikene til rad- og kolonnestyen ved oppstart. Hastigheten bestemmes avfrekvensen pa klokken som patrykkes. Simuleringene og testene som er utfrt viserat emulatoren gir et resultat som er visuelt likt reell foton-, rad- og kolonnesty,men styfordelingene er noe kunstige og kan forarsake uventede artifakter i bildene.

The Mandelbrot set, shown on the front page of this report, is perhaps themost well-known example of a fractal. Fractals is a certain familyof shapes with a very distinctive, interesting shape. The term was coined byBenoit B. Mandelbrot, for whom the Mandelbrot set is named after. The Mandelbrotset and other fractals are traditionally used for aesthetic purposes, such as inart, clothing, computer games, etc. However, there are also several practicalapplications for fractals, such as image compression.The Mandelbrot set is infinitely complex, making it desirable togenerate images of arbitrary sections of the set. Several software programs thatgenerate such images exists, but due to the computationally expensive nature ofthis task, these implementations are typically very slow, even on moderncomputers. However, the problem can be shown to be highly parallelizable,suggesting that a hardware implementation of such as generator should be able togenerate smooth real-time zoom animations, unlike existing softwareimplementations.A hardware fractal generator for the Mandelbrot set has been designed andimplemented in Verilog-2001. The design is very scalable, having a parameterspecifying the number of fractal point generators (cores) the synthesistool should implement. Furthermore, it is designed so that the floating pointunits in the cores are utilized nearly 100% of the time under normal operation.The design was tested on a Xilinx Virtex-6 FPGA with up to 16 cores, and it wasshown that the design was faster than a reference software solution running on adesktop computer when the number of cores was set to 2 or more.Additionally, a simplified Mandelbrot set algorithm is proposed and studiedexperimentally. In the simplified algorithm, the break condition in the algorithmloop is (|z_re| > 2) || (|z_im| > 2) as opposed to the standard |z| > 2.The images produced using the simplified algorithm was judged to be nearlyindistinguishable from those produced with the standard algorithm, and thereforepreferred as it is easier to implement.Finally some future work is proposed. The integration of the fractal generatorwith the Mali-400 GPU originally planned as part of this thesis is left asfuture work. It is also suggested to consider designing a custom fixed-pointformat for use internally in the fractal generator, as the standardbinary32 floating-point format (FP32) is shown to be badly suited forthis application.

Programvaredefinert radio (SDR) er ein ny måte å implementere radiosystem på. Hovudtanken er at delar av radioen som tidlegare har vore implementert med låste analoge og digitale løysingar skal erstattast med programvare som køyrer på ein prosessor. Dette kan forbetre mellom anna fleksibilitet, tilpassingsdyktigheit og produksjonskostnadar.Denne oppgåva tek for seg ein DSP-arkitektur spesielt tilpassa lågeffekt modulasjon og demodulasjon av radiosignaler med lav kompleksitet. Bluetooth er vald som døme og demodulasjonsdelen av denne er analysert for å belyse kva krav ein slik applikasjon vil stille til ein digital signalprosessor.Gjennom denne analyse kjem det fram at ein del av applikasjonen, estimasjon av arcus tangens, bør akselererast for å oppnå optimal yting og effektforbruk. Dette blir realisert gjennom å introdusere ei CORDIC-eining i systemet. Denne er så satt i samanheng med resten av prosessorarkitekturen, og det er sett på korleis dette påverkar krava til arkitekturen.Det blir mellom anna konkludert med at DSP-en bør innehalde ein dedikert løkkehandterar samt ein cache for programminnet.

With the introduction of low-power wireless technologies, new applicationsin the healthcare, fitness and home entertainment markets emergethrough the use of ultra low-power sensors. These devices are designed torun for years on a single coin-cell battery.ANT and Bluetooth Low Energy are two low-power protocols that emergeas competitors in this market. The ability to combine these in a single systemnot only takes away the element of choice from the manufacturers, but alsoprovides compatibility between the two protocols. An ANT-enabled devicecan be coupled to a Bluetooth network, with the benefit of connecting tonon-ANT central devices, such as smartphones, tablets and laptops.In this thesis, the co-existence of these two protocols is discussed. Animplementation with two distinct radios for each protocol, controlled by asingle embedded microcontroller, is presented. The implementation is testedwith regards to packet loss with a simple test application. Test results showthat the obtained packet loss cannot be correlated to the co-existence of thetwo protocols.

HDMI is the de facto global standard for connecting HD components and bridging the gap between consumer electronics and personal computer products, making it a priority to develop efficient hand-held, battery-powered units that support the standard.This is a study into how to design a low power and high performance system that can transmit HDMI-signals to a valid HDMI-receiver. The main priority is to implement the TMDS part of a HDMI-transmitter, where parallel data is encoded and serialized at high frequencies. The theory chapters provides an orderly summary of the complex workings of the HDMI-standard, in addition to an introduction to high-performance digital circuit design. This is followed by a system specification chapter, which sets the constraints of the design and discusses the hardware requirements. The subsequent chapter first deals with the design of a straightforward, basic HDMI-transmitter, before moving on to an enhanced design process. The basic design is used as a base for discussions in regard to how effective the suggested enhancement techniques are. The improvements result in an enhanced design able to operate at 742,5 MHz and support High-Definition video at the impressive resolution of 1080p30. This is achieved by using a 180nm, low-leakage library, and the final design consists of approximately 24.000 unit-sized transistor equivalents, consuming approximately a total of 13,6 mW.

The NTNU Test Satellite (NUTS) project is aiming to launch a 10×10×20 cm nanosatellite by the year 2014. The goal is to design and develope a low cost satellite by exploring the use of commersially available components. This work will focus on the power system of the NUTS satellite, which consists of a power distribution system, the backplane, and a power condition system, the Electrical Power System (EPS).This thesis describes the design and evaluation of the EPS module, which is a critical part of the satellite, because without power the satellite will not be able to operate. The electrical power system of the satellite consists of the solar cells, batteries, and voltage converters. With limited power available, the main focus of the design has been to implement an efficient system with minimum losses in power conversions.The Electrical Power System (EPS) module has been designed with simplicity, reliability, and redundancy in mind. The designed is based on the requirements of a reliable power source, with the main goals of charging the batteries with power from the solar cells and regulate the battery voltage down to the requested voltages of the backplane. A charger is chosen for its abilities to provide efficient and safe charging by using proper strategies for efficient energy harvesting and charging. To accommodate the voltage request of the backplane, four fixed value regulators is chosen for the design. For power monitoring of the provided power from the solar cells and batteries, current monitor sensors are implemented after each charger circuit and the batteries. Based on the specification of the solar cells and the batteries a final design of the main functionalities has been provided and a prototype of the EPS module has been produced.The proposed solution offers a reliable and redundant system, where a loss of one charger or converter will not mean the end of the mission. The EPS module has been tested and evaluated, and displays good performance results in terms of charging the batteries and voltage regulation. The efficiency of the EPS chargers is found to be 95 %.

The Mandelbrot set is a well-known fractal with mathematical propertiesthat can be exploited to create 3D-landscapes. The operations required tocalculate a heightmap using the Mandelbrot set are highly parallelizableand is thus suitable for a hardware implementation. Generation of 3D-landscapes,on-the-y, using the Mandelbrot set is desirable since the Mandel-brot set is innitely complex[4] and deterministic. This makes possible thecreation of many dierent landscapes with complex patters in, for example,computer games.A previous master thesis[4] presents a vertex array generator(VAG) thatgenerates the vertices of a 3D-landscape based on an area of the Mandelbrotset. This thesis explores dierent architectures that connect this vertex arraygenerator with the Mali-400 graphics processing unit(GPU). The result isthat the VAG in its current state is not suitable for integration, mostly sinceit does not support random access to vertices. Thus, a new fractal generatorarchitecture is presented, reusing parts of the VAG.The new fractal generator is implemented in Verilog and its functionalityis veried using the Universal Verication Methodology(UVM). Then, thefractal generator is integrated with the Mali-400 GPU in an FPGA frame-work and synthesized on FPGA. Tests are also performed at each step ofintegration.An OpenGL for Embedded Systems 2.0 demo is written to showcase thefunctionality of the fractal generator. Changes have been made to the Mali-400 drivers to automatically congure and set-up the fractal generator whilethe demo is running.The fractal generator is shown to be working as intended with a scalableperformance based on a number of internal cores. Using 64 cores the fractalgenerator has a worst-case frame time of 51.1 ms at 400Mhz which equals aframe rate of 450 frames pr second, vastly outperforming a software imple-mentation.The fractal generator is currently limited to creating landscapes of 128x128points, the intention was to use the demo and driver to increase the resolutionbut this has not been solved.Increasing the resolution and optimizing the cache size of the fractal generatorhas been left for future work.

Ray tracing of sparse voxel octrees is a method of rendering images of 3D models, which could soon become practical for use in real time applications. This is desirable as ray tracing can produce very realistic visualizations, while voxel models can represent models with very fine geometric detail. For these reason the method has attracted significant attention in recent years, but no hardware solution has been published yet. This thesis presents a design of ray tracing of sparse voxel octrees in hardware. The objective is to show if it is sensible to implement the method in hardware, and if it could be integrated on modern GPUs alongside rasterization. To this end, the techniques used in existing software implementations of this method is reviewed, and an algorithm suitable for hardware implementation is presented. The problems of integrating the method with rasterization is explored, and the algorithm is analyzed and optimized to improve efficiency in hardware. A software implementation is presented, which supports the development of a hardware design. This design is implemented using the Verilog hardware description language, and it has been simulated and synthesized for an FPGA prototype. Multiple versions of the design has been synthesized and tested, and to evaluate the impact of design parameters the test results from these designs is presented. The thesis provides a comprehensive evaluation of the proposed design, and the results indicate that the algorithm is well suited for hardware implementation. Although real-time performance was not achieved, there are indications that further optimizations should allow real-time performance on the same platform, and that a full scale implementation on a modern GPU could probably allow ray tracing with a quality which is competitive with rasterization.

In this thesis, both synchronous and asynchronous methodologies is explored for implementing a capacitive touch digital detection filter circuit.Asynchronous methodologies promise characteristics such as lower power, higher area cost and lower emission than synchronous methodologies. The aim of this thesis is to show if this can be exploited for this application.The synchronous implementation is written in Verilog, and follows a standard synchronous design flow. The asynchronous implementation is written in Balsa, and follows a Balsa Asynchronous Synthesis System design flow.Both implementations have been synthesised to netlist.A simple clock tree was generated for the synchronous implementation.Both netlists was simulated with wire load models.Netlist simulation of the synchronous and the asynchronous implementation shows that the power consumption is similar for the two implementations, because the fixed sample rate of the capacitance measurement operation dominates over the filter operations.The overhead from the handshake logic results in double the area for the asynchronous implementation. The asynchronous implementation has lower emission because of the randomness of the power consumption from the handshake circuits when the circuit is not sampling, while the synchronous implementation has large frequency components with harmonics from both clock flanks, resulting in higher emissions. Thus, asynchronous methodologies do not automatically lead to low power consumption, but can lead to larger area cost and lower emission.In addtion, new approaches for interfacing an asynchronous circuit, described in Balsa, with an analog circuit, and implementing a variable speed sampler clock with a minimum fixed sample period has been found, but not implemented.

To find the solution to large dense systems have always been a very time consuming problem, this thesis tries to accelerate this problem by implementing an highly pipelined conjugate gradient method on an FPGA, it has been used to solve dense systems of linear equations and has been tested and compared to a software version of the algorithm. The FPGA where capable of utilizing 90 % of the available memory bandwidth, in addition it is shown that the FPGA implemented Conjugate Gradient Method can be 30x faster compared to a custom made Conjugate Gradient method in software.