In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.