The continuous improvement in the speed of digital components in conjunction with reduction of size has brought about a revolutionary age of microprocessors. Mathematical functions, which at one time could only be implemented by complex analog circuitry, can now be easily implemented via microprocessors and high density digital components. Principles of random number generation must be understood in order to implement pseudo-random algorithms in a digital random frequency generator (DRFG) design. Chapter 1 is a discussion of several types of random number algorithms which have been used in the past and outlines the deficiencies and advantages associated with each individual algorithm. In particular, problems such a cycling and maximum period deficiency are discussed. The discussions in Chapter 1 lead to the selection of a random number algorithm which can be used in a DRFG design. There are other characteristics which should be observed in the evaluation of acceptable random number algorithms. In Chapter 2 three tests are described which can be applied in order to test the algorithm for the well-known uniformity and independence criteria. These tests are implemented in a Fortran program which is used to evaluated the algorithm selected in Chapter 1. The random number generator evaluation program (RNGEP) listing is presented in Appendix B. The results of the tests applied to the DRFG random number algorithm are presented in Appendix C.

Analysis and comparison of nine different Hardware Description Languages is presented. Comparison features are discussed and each language is analysed according to the comparison features, which are: sequencing mechanisms, applicability to generic structures, abstraction of data and operation, timing mode, communication mechanisms, and instantiation and interconnection of elements. Based on the analysis of the languages, optimal constructs for chip level modeling are extracted. Example descriptions of a microprocessor system MARK 2 are presented. / M.S.

The circular BIST design is a technique in which the existing circuit is modified, so that the processes of test generation and response compaction are carried out by the circuit being tested itself. Most response compaction techniques suffer from loss of information, known as aliasing. Aliasing is said to occur in a response compaction technique when the response generated by the circuit, under the presence of a fault, is different from its fault-free response, but this information is later lost during compaction, and the faulty compacted response at the end of the test session is identical to the fault-free compacted response. A program to synthesize circular BIST hardware on general sequential circuits has been developed. A parallel fault simulator has been developed to detect aliasing errors in circular BIST design. Experimental results on aliasing probability in circular BIST design are reported for twenty-three sequential benchmark circuits. / Master of Science

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

No description available.

by Tai Leong Charn. / Bibliography: leaves R-i-iii / Thesis (M.Phil.)--Chinese University of Hong Kong, 1983

Xiao, Zigang. / "October 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 62-66). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.vi / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Microfluidic Technology --- p.2 / Chapter 1.1.1 --- Continuous Flow Microfluidic System --- p.2 / Chapter 1.1.2 --- Digital Microfluidic System --- p.2 / Chapter 1.2 --- Pin-Constrained Biochips --- p.4 / Chapter 1.2.1 --- Droplet-Trace-Based Array Partitioning Method --- p.5 / Chapter 1.2.2 --- Broadcast-addressing Method --- p.5 / Chapter 1.2.3 --- Cross-Referencing Method --- p.6 / Chapter 1.2.3.1 --- Electrode Interference in Cross-Referencing Biochips --- p.7 / Chapter 1.3 --- Computer-Aided Design Techniques for Biochip --- p.8 / Chapter 1.4 --- Placement Problem in Biochips --- p.8 / Chapter 1.5 --- Droplet Routing Problem in Cross-Referencing Biochips --- p.11 / Chapter 1.6 --- Our Contributions --- p.14 / Chapter 1.7 --- Thesis Organization --- p.15 / Chapter 2 --- Literature Review --- p.16 / Chapter 2.1 --- Introduction --- p.16 / Chapter 2.2 --- Previous Works on Placement --- p.17 / Chapter 2.2.1 --- Basic Simulated Annealing --- p.17 / Chapter 2.2.2 --- Unified Synthesis Approach --- p.18 / Chapter 2.2.3 --- Droplet-Routing-Aware Unified Synthesis Approach --- p.19 / Chapter 2.2.4 --- Simulated Annealing Using T-tree Representation --- p.20 / Chapter 2.3 --- Previous Works on Routing --- p.21 / Chapter 2.3.1 --- Direct-Addressing Droplet Routing --- p.22 / Chapter 2.3.1.1 --- A* Search Method --- p.22 / Chapter 2.3.1.2 --- Open Shortest Path First Method --- p.23 / Chapter 2.3.1.3 --- A Two Phase Algorithm --- p.24 / Chapter 2.3.1.4 --- Network-Flow Based Method --- p.25 / Chapter 2.3.1.5 --- Bypassibility and Concession Method --- p.26 / Chapter 2.3.2 --- Cross-Referencing Droplet Routing --- p.28 / Chapter 2.3.2.1 --- Graph Coloring Method --- p.28 / Chapter 2.3.2.2 --- Clique Partitioning Method --- p.30 / Chapter 2.3.2.3 --- Progressive-ILP Method --- p.31 / Chapter 2.4 --- Conclusion --- p.32 / Chapter 3 --- CrossRouter for Cross-Referencing Biochip --- p.33 / Chapter 3.1 --- Introduction --- p.33 / Chapter 3.2 --- Problem Formulation --- p.34 / Chapter 3.3 --- Overview of Our Method --- p.35 / Chapter 3.4 --- Net Order Computation --- p.35 / Chapter 3.5 --- Propagation Stage --- p.36 / Chapter 3.5.1 --- Fluidic Constraint Check --- p.38 / Chapter 3.5.2 --- Electrode Constraint Check --- p.38 / Chapter 3.5.3 --- Handling 3-pin net --- p.44 / Chapter 3.5.4 --- Waste Reservoir --- p.45 / Chapter 3.6 --- Backtracking Stage --- p.45 / Chapter 3.7 --- Rip-up and Re-route Nets --- p.45 / Chapter 3.8 --- Experimental Results --- p.46 / Chapter 3.9 --- Conclusion --- p.47 / Chapter 4 --- Placement in Cross-Referencing Biochip --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.50 / Chapter 4.3 --- Overview of the method --- p.50 / Chapter 4.4 --- Dispenser and Reservoir Location Generation --- p.51 / Chapter 4.5 --- Solving Placement Problem Using ILP --- p.51 / Chapter 4.5.1 --- Constraints --- p.53 / Chapter 4.5.1.1 --- Validity of modules --- p.53 / Chapter 4.5.1.2 --- Non-overlapping and separation of Modules --- p.53 / Chapter 4.5.1.3 --- Droplet-Routing length constraint --- p.54 / Chapter 4.5.1.4 --- Optical detector resource constraint --- p.55 / Chapter 4.5.2 --- Objective --- p.55 / Chapter 4.5.3 --- Problem Partition --- p.56 / Chapter 4.6 --- Pin Assignment --- p.56 / Chapter 4.7 --- Experimental Results --- p.57 / Chapter 4.8 --- Conclusion --- p.59 / Chapter 5 --- Conclusion --- p.60 / Bibliography --- p.62

Spectral methods have been used for many applications in digital logic design, digital signal processing and telecommunications. In digital logic design they are implemented for testing of logical networks, multiplexer-based logic synthesis, signal processing, image processing and pattern analysis. New developments of more efficient algorithms for spectral transformations (Rademacher-Walsh, Generalized Reed-Muller, Adding, Arithmetic, multiple-valued Walsh and multiple-valued Generalized Reed- Muller) their implementation and applications will be described.

Graduation date: 1991

Graduation date: 1991