<p>Ett digitalt vågfilter av Richardstyp har implementerats i en FPGA på ett utvecklingskort. Sampel kan skickas till filtret och mottas från filtret via serieporten på en dator. Metoden som användes är att en modell av filtret konstruerades i Simulink. Filtret har modifierats med avseende på skalning, brus och stabilitet. VHDL-koden till filtret genererades i Simulink genom att bygga modellen av Xilinx Blockset. Ytterligare VHDL-kod konstruerades för att kunna skicka sampel mellan filter och minnet på utvecklingskortet. För kommunikation mellan minnet på utvecklingskortet och dator utnyttjades färdiga lösningar.</p> / <p>Filtrets funktion efter implementeringen var samma som modellens byggd i Simulink. A Richards’ structure wave digital filter has been implemented on an evaluation board in an FPGA. Samples can be sent to the filter and received from the filter using the serial port of a computer. The method used is that a modell of the filter has been created in Simulink. The filter has been modified with respect to scaling, noise and stability. VHDL for the filter has been generated in Simulink by using Xilinx blockset to build the modell. Also, VHDL has been constructed to be able to send samples between the filter and the memory on the evaluationboard. For communication between the memory on the evaluationboard and the computer, existing solutions have been used. The functionality of the filter after implementation was the same as in the modell built in Simulink.</p>

In this thesis we discuss the design and implementation of Digital Signal Processing (DSP) applications in a standard digital CMOS technology. The aim is to fulfill a throughput requirement with lowest possible power consumption. As a case study a frequency selective filter is implemented using a half-band FIR filter and a bireciprocal Lattice Wave Digital Filter (LWDF) in a 0.35 µm CMOS process. The thesis is presented in a top-down manner, following the steps in the topdown design methodology. This design methodology, which has been used for bit-serial maximally fast implementations of IIR filters in the past, is here extended and applied for digit-serial implementations of recursive and non-recursive algorithms. Transformations such as pipelining and unfolding for increasing the throughput is applied and compared from throughput and power consumption points of view. A measure of the level of the logic pipelining is developed, i.e., the Latency Model (LM), which is used as a tuning variable between throughput and power consumption. The excess speed gained by the transformations can later be traded for low power operation by lowering the supply voltage, i.e., architecture driven voltage scaling. In the FIR filter case, it is shown that for low power operation with a given throughput requirement, that algorithm unfolding without pipelining is preferable. Decreasing the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. The digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput. In the bireciprocal LWDF case, the LM order can be used as a tuning variable for a trade-off between low energy consumption and high throughput. In this case using LM 0, i.e., non-pipelined processing elements yields minimum energy consumption and LM 1, i.e., use of pipelined processing elements, yields maximum throughput. By introducing some pipelined processing elements in the non-pipelined filter design a fractional LM order is obtained. Using three adders between every pipeline register, i.e., LM 1/3, yields a near maximum throughput and a near minimum energy consumption. In all cases should the digit-size be equal to the number of fractional bits in the coefficient. At the arithmetic level, digit-serial adders is designed and implemented in a 0.35 µm CMOS process, showing that for the digit-sizes, , the Ripple-Carry Adders (RCA) are preferable over Carry-Look-Ahead adders (CLA) from a throughput point of view. It is also shown that fixed coefficient digitserial multipliers based on unfolding of serial/parallel multipliers can obtain the same throughput as the corresponding adder in the digit-size range D = 2...4. A complex multiplier based on distributed arithmetic is used as a test case, implemented in a 0.8 µm CMOS process for evaluation of different logic styles from robustness, area, speed, and power consumption points of view. The evaluated logic styles are, non-overlapping pseudo two-phase clocked C2MOS latches with pass-transistor logic, Precharged True Single Phase Clocked logic (PTSPC), and Differential Cascade Voltage Switch logic (DCVS) with Single Transistor Clocked (STC) latches. In addition we propose a non-precharged true single phase clocked differential logic style, which is suitable for implementation of robust, high speed, and low power arithmetic processing elements, denoted Differential NMOS logic (DN-logic). The comparison shows that the two-phase clocked logic style is the best choice from a power consumption point of view, when voltage scaling can not be applied and the throughput requirement is low. However, the DN-logic style is the best choice when the throughput requirements is high or when voltage scaling is used.

This work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.

The complicated turbulence structures in wall-bounded flows require accurate subgrid scale, SGS, modelling and realistic inlet boundary conditions for Large Eddy Simulation, LES. The present study focused on the investigation and development of transport equation SGS models and on the development of inlet conditions generation algorithms specialised for LES of wall-bounded flows. The investigation of SGS models has been carried out in two stages. In the first stage, models based on resolved scales and models based on subgrid scales were tested on a series of channel flow cases. Among the second group of models, there was a new SGS model whose development was based on the concept of dissipation calculated from the energy spectrum. The results indicated the superiority of the models based on subgrid scales, with the new model providing the most accurate flow field in general. (Continues...).

Variable digital filters (VDF) find many application areas in communication, audio, speech and image processing. This thesis analyzes design and implementation of FIR digital filters with variable frequency characteristics and introduces two design methods. The design and implementation of the proposed methods are realized on Matlab software program. Various filter design examples and comparisons are also outlilned. One of the major application areas of VDFs is software defined radio (SDR). The interpolation problem on sample rate converter (SRC) unit of the SDR is solved by using these filters. Realizations of VDFs on SRC are outlined and described. Simulations on Simulink and a specific hardware are examined.

The paper deals with analysis of the problems of digital signal processing and with design of the control unit for DSP and audio signal distribution to active external loudspeakers. It describes function of delta-sigma AD converters, the most widely used digital filters and Fast Fourier Transform. The processed signal will be send to external loudspeakers using an Ethernet interface. The paper also covers the design of signal processing unit's hardware and software. Achieved functions and parameters of the unit are discussed in conclusion.

No description available.

Neste trabalho se apresenta o desenvolvimento de algoritmos hermitianos de integração das equações diferenciais do filtro digital de Butterworth mediante operadores de integração numérica de ordem elevada com passo único. A teoria do filtro de Butterworth é apresentada mediante o emprego da transformada de Fourier. Exemplos de aplicação apresentados através destes algoritmos mostram que os resultados são, como esperado, mais precisos que os resultantes dos métodos usuais presentes na literatura especializada / In this work is presented the development of hermitian algorithm for integration of the Butterworth digital filter’s differential equations by means of high order numerical one step operators. The Butterworth filter’s theory is presented based on the Fourier transform. Numerical examples show that the results of the developed hermitian algorithm are more accurate than the usual methods present in the specialized literature, as expected

<div>The objective of this doctoral research was to develop a versatile inverse heat transfer approach, that would enable the solution of small scale problems present in microelectronics, as well as the analysis of the complex heat flux in turbines. An inverse method is a mathematical approach which allows the resolution of problems starting from the solution. In a direct problem, the boundary conditions are given, and using the governing physics principles and equations you can calculate the solution or physical effect. In an inverse method, the solution is provided and through the physical equations, the boundary conditions can be determined. Therefore, the inverse method applied to heat transfer means that we know the variation of temperature (effect) over time and space. With the temperature input, the geometry, thermal properties of the test article and the heat diffusion equation, we can compute the spatially- and temporally-varying heat flux that generated the temperature map.</div><div><br></div><div>This doctoral dissertation develops two inverse methodologies: (1) an optimization methodology based on the conjugate gradient method and (2) a function specification method combined with a regularization technique, which is less robust but much faster. We implement these methodologies with commercial codes for solving conductive heat transfer with COMSOL and for conjugate heat transfer with ANSYS Fluent.</div><div><br></div><div>The goal is not only the development of the methods but also the validation of the techniques in two different fields with a common purpose: quantifying heat dissipation. The inverse methods were applied in the micro-scale to the dissipation of heat in microelectronics and in the macro-scale to the gas turbine engines.<br></div><div><br></div><div>In microelectronics, we performed numerical and experimental studies of the two developed inverse methodologies. The intent was to predict where heat is being dissipated and localized hot spots inside of the chip from limited measurements of the temperature outside of the chip. Here, infrared thermography of the chip surface is the input to the inverse methods leveraging thermal model of the chip. Furthermore, we combined the inverse methodology with a Kriging interpolation technique with genetic algorithm optimization to optimize the location and number of the temperature sensors inside of the chip required to accurately predict the thermal behavior of the microchip at each moment of time and everywhere.<br></div><div><br></div><div>In the application for gas turbine engines, the inverse method can be useful to detect or predict the conditions inside of the turbine by taking measurements in the outer casing. Therefore, the objective is the experimental validation of the technique in a wind tunnel especially designed with optical access for non-contact measurement techniques. We measured the temperature of the outer casing of the turbine rotor with an infrared camera and surface temperature sensors and this information is the input of the two methodologies developed in order to predict which the heat flux through the turbine casing. A new facility, specifically, an annular turbine cascade, was designed to be able to measure the relative frame of the rotor from the absolute frame. In order to get valuable data of the heat flux in a real engine, we need to replicate the Mach, Reynolds, and temperature ratios between fluid and solid. Therefore, the facility can reproduce a large range of pressures and flow temperatures. Because some regions of interest are not accessible, this researchprovides a significant benefit for understanding the system performance from limited data. With inverse methods, we can measure the outside of objects and provide an accurate prediction of the behavior of the complete system. This information is relevant not only for new designs of gas turbines or microchips, but also for old designs where due to lack of prevision there are not enough sensors to monitor the thermal behavior of the studied system.<br></div><div><br></div>

A ciência na qual se estuda a deformação de um fluido no qual é aplicada uma tensão de cisalhamento é conhecida como reologia e o equipamento utilizado para a realização dos ensaios é chamado de reômetro. Devido a impraticabilidade de uso de reômetros comerciais, diversos pesquisadores desenvolveram reômetros capazes de analisar suspensões de macropartículas, baseados nos mesmos princípios de funcionamento dos equipamentos já existentes. Em alguns casos, a medição do torque do motor é realizada pela aquisição da tensão, uma vez que esta é proporcional ao torque. Entretanto, para melhor compreensão do resultado e para evitar a possibilidade de conclusões precipitadas, vê-se necessária correta interpretação do sinal elétrico, precisando avaliar qual frequência do sinal é relevante para o ensaio e, também, qual a melhor taxa de amostragem. Além da aquisição, para que o ensaio reológico seja realizado com precisão, é indispensável ótimo controle da taxa ou tensão do motor e uma alternativa é a utilização de um servomotor e um servoconversor. No caso desse ser comercial é essencial saber configurá-lo. Para facilitar o usuário leigo, alguns pesquisadores desenvolveram softwares para controle do equipamento e análise dos dados. Assim, o presente trabalho tem como objetivo propor uma metodologia para compreender o sinal aquisitado de um reômetro servo controlado e desenvolvimento do software de análise para o tratamento dos dados obtidos a partir de ensaios reológicos. Verificou-se a melhor configuração do servocontrolador, a melhor taxa de amostragem, de no mínimo 20 amostras/segundo, e, também, desenvolveu-se um filtro digital passa-baixa do tipo FIR para remover a frequência indesejada. Além disso, foi desenvolvido um software utilizando uma rotina em Matlab e uma interface gráfica do usuário (Graphical User Interface - GUI), para o pós-processamento dos dados para auxiliar o usuário leigo no tratamento e interpretação do resultado, que se mostrou eficaz. / Rheology is the study of the behavior of material in fluid state. Rheometer is the equipment used to perform rheological measurements. Because of the impracticability of commercial rheometer, many researchers have developed rheometer able to analyze macro particles suspension, based on the principle of operation of the existing equipment. In some cases, measurement of the motor torque is performed by acquiring voltage signal, since is proportional to torque. However, for better understanding of the rheological results, it is necessary to understand the electrical signal, evaluating which signal frequency is relevant and what is the best sample rate. In addition, for an accurate rheological testing, it is essential a precise control of the shear rate or shear stress of the motor and a good alternative is the use of a servomotor and a drive. In the case of the drive being commercial, it is essential to know how to configure it. To turn rheometer user-friendly, some researchers have developed software to control the equipment and to analyze data. Thus, this dissertation propose a methodology to understand the electrical signal of a servo controlled rheometer and development of analysis software to process the data obtained from rheological tests. It has been found the best configuration of the servo drive, minimum sampling rate of 20 samples/second, and development of a low pass digital filter to remove unwanted frequency. In addition, was developed a software using a Matlab routine and a Graphical User Interface (GUI) to assist the user in the processing and interpretation of the result.