Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data. A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4£c-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost. The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power. Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design. The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced. Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.

In the current development work conducted at BAE Systems Hägglunds AB's electronics department, there are often long lead times from started projects to finished electronic units. This means that it is necessary to take a new approach to development in order to meet changing specifications and new interfaces. To mitigate the risks in design and interfaces, testing of the system needs to start as early as possible. Against the given background, the aim of the project is to develop and evaluate a modular concept for different Input/output (I/O) interfaces between a carrier board and modules. The modular concept where developed using Altium Designer and through schematic design and PCB design the designs was developed for the intended concept regarding modularization. To test the connections between the carrier board and modules and to get a visual picture over how it could look, Altium designers Multi-board Assembly function where used. By analyzing the boundaries between the carrier board and I/O-modules, new limitations were discovered in the contact surfaces between them. The focus turned to improve the existing carrier board by replacing the existing connectors with more modular alternative connectors that better fits the intended concept of the modularity in the I/O-modules. Three different alternatives for the current carrier board were evaluated and the alternative that is the best for modularization is to change the connectors on the current carrier board. The design of the I/O-modules are based on the already existing I/O designs and the I/O-modules designed were Digital Input (DIP) and Digital Output (DOP). The results that emerged during the project are as follows: The designed I/O-modules follow a relationship-based design to produce a combination of the different circuit solution already available at BAE Systems. The circuits DIP and DOP are the most common I/O-interfaces in use and the focus was to develop modules for these. In order to achieve the optimal modularity with respect for the intended concept, the current design of the carrier boards need to change to meet the intended concept regarding modularization. / I det nuvarande utvecklingsarbetet som bedrivs på BAE Systems Hägglunds ABs elektronikavdelning finns det ofta långa ledtider från påbörjade projekt till färdiga elektronikenheter. Detta leder till att omtag i utvecklingen blir nödvändigt för att kunna möta ändrade specifikationer och nya gränsytor. För att mitigera risker i design och gränsytor behöver testning av systemet påbörjas så tidigt som möjligt. Projektet syftar mot den givna bakgrunden att ta fram och utvärdera ett modulärt koncept för olika Input/Output (I/O) gränssnitt mellan bärarkort och moduler. Det modulära konceptet utvecklades i Altium Designer och genom schemaritning och PCB design utvecklades designerna för det tänkta konceptet gällande modularisering. För att testa anslutningar mellan bärarkort och modul och samtidigt få en visuell bild över hur resultatet kan se ut, användes Altium Multi-board Assembly. Genom att analysera avgränsningar mellan bärarkort och I/O-modul upptäcktes nya begränsningar i kontaktytorna mellan dem. Fokus hamnade på att förbättra det befintliga bärarkortet genom att byta ut de befintliga kontakterna till mer modulära kontakter som passar det tänkta konceptet för I/O-modulernas modularitet. Tre olika alternativ för det nuvarande bärarkortet togs upp och det alternativ som är bäst sett till Modularisering är att ändra de kontakter som finns på det nuvarande bärarkortet. Designen av I/O-modulerna utgick ifrån de redan befintliga kretslösningar som finns framtagen och de I/O-moduler som designades var Digital input (DIP) och Digital Output (DOP). De resultat som kom fram genom projektet är följande: De I/O-moduler som framställts följer en relationsbaserad design för att framställa en kombination av de olika kretslösningar som redan finns framtagen av BAE Systems. Kretsarna DIP och DOP är de vanligaste I/O-gränssnitten som används och fokus blev att ta fram moduler för dessa. För att uppnå optimal modularitet med anseende på det tänkta konceptet behöver den nuvarande designen av bärarkortets kontakter ändras för att kunna möta den optimala modulariteten för det tänkta konceptet.

The thesis deals with the design of digital I/O card with USB connectivity for Honeywell spol. s r.o. – HTS CZ o.z. company. The main objective is the delay elimination between reading the current state of the inputs and outputs setting which occurs on the actual used commercial card. Further initial analysis outlines possible solutions at the beginning of the work. One of chapters describes USB communication interface, including its com- munications protocol and USB driver implementation on the operating system Microsoft Windows. The digital card has four I/O ports consisting of eight lines. All ports have built-in protection against overcurrent and ESD protection. Digital isolator is used for USB. Power is supplied via USB, but it is optionally possible to connect an external power source. The last part of the thesis is focused on the card driver design.