Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references (leaves 244-266). Available also in an electronic version.

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 85-87).

Massachusetts Institute of Technology Electronic Systems Laboratory Department of Electrical Engineering. / Bibliography: p. 27-29. / NASA research grant NsG-496 M.I.T. Projects DSR 76152

Massachusetts Institute of Technology Electronic Systems Laboratory Department of Electrical Engineering. / Bibliography: p. 16-20. / NASA research grant NsG-496 M.I.T. Projects DSR 76152

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Today’s digital communication systems perform data transfers at the rate of millions of bits per minute, with data errors in the order of l/6th error per day. This magnitude of errorless communication is now possible because of sophisticated error correcting codes. Many types of error codes are employed today in three distinct areas of digital data communication: human to computer; data source to computer; computer to computer; and intra-computer; we are concerned here with intra-computer communication. This research is primarily a mathematical study of error codes in general to explore the possibilities of each major type for the purpose of implementation in real systems. The author was inspired toward this goal by several people and self-feelings. The first, was a definite affinity toward orderliness and the logical sequence of formal mathematics. Secondly, the thrusting of being assigned to a work project where computer maintenance and where all types of errors became important. And, finally an advisor who believes in “practical things”. The original portion of this endeavor is to be found in the conclusions drawn from each group of mathematical facts disclosed in the research. The particular bend of the author toward the cost/reliability/ efficiency of the system was not the intent of the theoretical mathematicians who did the majority of the work quoted herein. The author's contribution was to draw these ideas and works together and to form the conclusions based upon his experience and training as an Engineer. The primary conclusion is that multi-residue systematic codes appear to be the best choice for implementation of all around error correction and general hardware configurations. This conclusion is within the constraints that were laid down in the introduction of the research; 1) to not increase the cost of hardware, 2) to maintain or improve the system reliability, and 3) to maintain or increase the processing speed.

Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization with respect to asynchronous circuits, and ties the results into the STA solution of USC. The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and light in power. They have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP circuits excellent candidates for modern many-core, concurrent network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a `single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, the results of this work will provide confidence in the correct operation of GasP circuits.

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No description available.

This paper demonstrates conversion of an analog filter into a digital filter using computer aided software. The filter design to be demonstrated is a common third order Butterworth filter. This paper is not an attempt to review all filter designs or applications, but rather the attempt is to give a detailed explanation of the steps required to design almost any digital filter. No knowledge of the Intel Series 210 microcomputer development system is assumed. The appendices contain introduction to the Series 210 system. Chapter I demonstrates the steps needed to design this filter without computer aid. Included are both analog and digital filter response characteristics. Chapter II supplemented with Appendix C demonstrates the computer aided filter design. Again, filter characteristics are included. Chapter III compares the results of Chapter I and II. Even though this paper attempts to be inclusive of most of the computer details, it should not be used in exclusion of the available Series 210 manuals.