No description available.

No description available.

In this thesis a binary digital system, capable of performing arithmetic operations, was developed from a simple two-state (binary digital) device. This binary digital system or digital computer could be programmed to add, subtract or multiply and perform many other logic functions. The above operations are performed serially in seven bit shift registers. The system is manually programmed using an Instruction Select Switch. During each phase of the development of the system, an example of the procedure used to reach a conclusion during that phase was explained at length. It is hoped that following and continually reapplying the basic procedures outlined in this thesis, particularly in the development of the Full Adder, would allow for the design of any moderately complex digital system. / Master of Science

M. S.

M. S.

No description available.

This thesis describes the design and implementation of a system called the Model Generator that graphically models digital system specifications expressed in English. This research is part of the ASPIN project which has a long-term goal of providing an automated system for digital system synthesis from informal specifications. Because of the versatility of the English language, there can be more than one interpretation of specification sentences. So before these specifications are synthesized into formal models, it is necessary to obtain validation of their interpretation from the specification author. The specification sentences are mapped into a common knowledge representation, called conceptual graphs, by first parsing and then semantically analyzing them. The Model Generator then uses the conceptual graphs to generate a graphical model representing the meaning of the English specification sentence. This is done in two stages. First, the commands for drawing the icons used for the graphical representation are assembled by consulting an Interpretation Library and a conceptual type hierarchy. In the second stage, the icons used in the representation are displayed using an X-Windows interface. The Model Generator has been implemented in the C programming language under the X-Windows environment. / Master of Science

Hardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.

by Lo Wing-yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves vii-ix). / ABSTRACT --- p.i / LIST OF TABLES --- p.iv / LIST OF FIGURES --- p.v / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Traditional Design Prototyping --- p.1 / Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2 / Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5 / Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6 / Chapter 2. --- HARDWARE DESIGNS --- p.9 / Chapter 2.1 --- Bus Interconnection --- p.9 / Chapter 2.1.1 --- Fixed buses --- p.9 / Chapter 2.1.2 --- Programmable buses --- p.12 / Chapter 2.2 --- Architectural Features --- p.15 / Chapter 2.2.1 --- Field programmable gate array --- p.15 / Chapter 2.2.2 --- Microprocessor --- p.15 / Chapter 2.2.3 --- Memory --- p.16 / Chapter 2.2.4 --- Buffers --- p.18 / Chapter 3. --- SOFTWARE TOOLS --- p.20 / Chapter 3.1 --- Critical Path Analysis --- p.20 / Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21 / Chapter 3.1.2 --- Computation time --- p.21 / Chapter 3.2 --- Circuit Partitioning --- p.23 / Chapter 3.2.1 --- Partitioning algorithm --- p.24 / Chapter 3.2.2 --- Effects of partitioning --- p.36 / Chapter 3.2.3 --- Partitioning parameters --- p.38 / Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39 / Chapter 3.3 --- IO Assignments --- p.40 / Chapter 3.3.1 --- Connect 4 FPGAs --- p.40 / Chapter 3.3.2 --- Connect 3 FPGAs --- p.42 / Chapter 3.3.3 --- Connect 2 FPGAs --- p.44 / Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47 / Chapter 3.4 --- Other Tools --- p.48 / Chapter 4. --- STRUCTURE ANALYSIS --- p.49 / Chapter 5. --- RESULTS --- p.52 / Chapter 6. --- FUTURE DIRECTION --- p.73 / Chapter 6.1 --- Other Possible Configurations --- p.73 / Chapter 6.2 --- Programmable Interconnection --- p.73 / Chapter 6.3 --- Expandability of UPB --- p.74 / Chapter 7. --- CONCLUSION --- p.75 / BIBLIOGRAPHY --- p.vii / APPENDICES --- p.x

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND AERO / Bibliography: leaves B1-B6. / by Michael Roy Mantz. / M.S.