Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.60-63).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Swaminatham, Madhavan.

Thesis (MS)--Montana State University--Bozeman, 2009. / Typescript. Chairperson, Graduate Committee: Brock LaMeres. Includes bibliographical references (leaves 64-66).

Thesis (Ph. D.)--Drexel University, 2004. / Includes abstract and vita. Includes bibliographical references (leaves 185-190).

The reliable construction of VLSI integrated circuits (ICs) requires that the ICs be tested after fabrication. An alternative to performing external testing is to create ICs that can test themselves with a built-in self-test (BIST) mode. Unfortunately the problem of embedding a self-test operating mode to the functional design is difficult for two reasons. (1) The creation of test sets that effectively test digital circuits requires the solution of several intractable problems. (2) The hardware resources dedicated to self-test are usually constrained. Modifications to the Logic III hardware description language and a new computer-aided design (CAD) tool, 1g3, are presented in this dissertation as an environment that allows BIST embedding to be created and evaluated. The major premise behind this work is that BIST design can be treated in a similar fashion as functional design, and that the designer can address the constraints of a BIST mode at the same time as the functional constraints. The modified language, called Logic III(UVic), allows BIST embeddings to be specified by an embedding module which describes how the circuit's memory elements are realized. This dissertation presents a library of embedding modules that realize several of the most common BIST architectures. Case studies using this environment are presented for an ALU, CORDIC, GCD, and string matching circuits. A BIST mode with almost 100% single stuck-at fault coverage is realized for each circuit. This shows that the CAD environment can be used to create self-testing circuits. In addition to aiding users in embedding BIST functionality, the 1g3 tool can be used to evaluate specific BIST architectures. Properties of BIST test pattern generators are presented that are used in analyzing the effectiveness of the generators for delay-fault testing. A novel approach based on creating a deterministic finite automaton that recognizes the fault-free responses is presented. / Graduate

This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new, portable Virtual-Reconfigurable-Circuit architecture—is a practical and viable evolution platform. Secondly, the research looks into two possible ways of making EHW systems more scalable: by optimising the system’s genetic algorithm; and by decomposing the solution circuit into smaller, evolvable sub-circuits or modules. GA optimisation is done is by: omitting a canonical GA’s crossover operator (i.e. by using an algorithm); applying evolution constraints; and optimising the fitness function. The circuit decomposition is done in order to demonstrate modular evolution. Three two-bit multiplier circuits and two sub-circuits of a simple, but real-world control circuit are evolved. The results show that the evolved multiplier circuits, when compared to a conventional multiplier, are either equal or more efficient. All the evolved circuits improve two of the four critical paths, and all are unique. Thus, it is experimentally shown that the V-FPGA is a viable hardware-platform on which hardware evolution can be implemented; and how hardware evolution is able to synthesise novel, optimised versions of conventional circuits. By comparing the and canonical GAs, the results verify that optimised GAs can find solutions quicker, and with fewer attempts. Part of the optimisation also includes a comprehensive critical-path analysis, where the findings show that the identification of dependent critical paths is vital in enhancing a GA’s efficiency. Finally, by demonstrating the modular evolution of a finite-state machine’s control circuit, it is found that although the control circuit as a whole makes use of more than double the available hardware resources on the V-FPGA and is therefore not evolvable, the evolution of each state’s sub-circuit is possible. Thus, modular evolution is shown to be a successful tool when dealing with scalability.

In general, it is difficult to automatically detect faults within large scale engineering plants early during their onset. This is due to a number of factors including the large number of components typically present in such plants and the complex interactions of these components, which are typically poorly understood. Traditionally, fault detection within these plants has been performed through the use of status monitoring systems employing limit checking fault detection. In this approach, upper and lower bounds are placed on what is prescribed as “normal” behaviour for each of the plant's collected status data signals and fault flags are generated if and when the given status data signal exceeds either of its bounds. This approach tends to generate relatively large numbers of false alarms, due to the technique's inability to model known signal dependencies, and it also tends to produce inconsistent fault flags, in the sense that the flags do not tend to be produced throughout the “fault” event. The limit checking approach also is not particularly adept at early fault detection tasks since as long as the given status data signal remains between the upper and lower bounds any signal behaviour is deemed as acceptable. Hence, behavioural changes in the status data signals go undetected until their severity is such that either the upper or lower bounds are exceeded. In this dissertation, two novel fault detection methodologies are proposed which are better suited to the early fault detection task than traditional limit checking. The first technique is directed at modeling of signals exhibiting unknown linear dependencies. This detection system utilizes fuzzy membership functions to model signal behaviour and through this modelling approach fault detection bounds are generated which meet a prescribed probability of false alarm rate. The second technique is directed at modelling signals exhibiting unknown non-linear, dynamic dependencies. This system utilizes recurrent neural network technology to model the signal behaviours and prescribed statistical methods are employed to determine appropriate fault detection thresholds. Both of these detection systems have been designed to be able to be retrofitted into existing industrial status monitoring system and, as such, they have been designed to achieve good modelling performance in spite of the coarsely quantized status data signals which are typical of industrial status monitoring systems constructed to employ limit checking. The fault detection properties of the proposed fault detection systems were also compared to an in situ limit checking fault detection system for a set of real-world data obtained from an operational large scale engineering plant. This comparison showed that both of the proposed fault detection systems achieved marked improvements over traditional limit checking both in terms of their false alarm rates and their fault detection sensitivities. / Graduate

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yes / Engineering undergraduates not only need to learn facts, but also how to be creative in the open-ended situations they will encounter in their professional careers. Our final year Honours module gives students a grounding in digital systems design, mainly using VLSI for design entry and simulation. The second half of our module is a design exercise, which has straightforward aspects, but which allows motivated students to undertake progressively open-ended investigations. Our educational framework is guided by recommendations of professional bodies promoting excellence and encouragement of creativity in engineering development. (C) 2013 The Authors. Published by Elsevier Ltd.

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