This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

by Cheng King Sum Frankie. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaf 53). / Acknowledgments --- p.iv / List of Figures --- p.vii / List of Tables --- p.ix / Abstract --- p.x / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Multiple Clock System --- p.1 / Chapter 1.2 --- Clock Multiplier --- p.2 / Phase-Locked Loop --- p.2 / Delay Locked Loop --- p.3 / Chapter 1.3 --- Objective --- p.5 / Chapter Chapter2 --- All-Digital Clock Multiplier --- p.6 / Chapter 2.1 --- Architecture --- p.6 / Chapter 2.2 --- Operation --- p.7 / Chapter 2.3 --- Implementation --- p.9 / Control Circuit --- p.9 / Phase-Locked Circuit --- p.11 / Frequency Detector --- p.12 / Frequency Divider --- p.13 / Synchronize Logic --- p.14 / DCO Control --- p.15 / Chapter Chapter3 --- Digitally-Controlled Oscillator --- p.16 / Chapter 3.1 --- Principle --- p.16 / Chapter 3.2 --- Design --- p.18 / Transient Analysis --- p.18 / Simulation result --- p.26 / Chapter 3.3 --- Layout --- p.30 / Chapter 3.4 --- Summary --- p.32 / Chapter Chapter4 --- Test and Measurement --- p.34 / Chapter 4.1 --- Digitally-Controlled Oscillator Characteristics --- p.34 / Chapter 4.2 --- All-Digital Clock Multiplier Characteristics --- p.43 / Chapter Chapter5 --- Conclusions --- p.51 / Chapter 5.1 --- Summary --- p.51 / Chapter 5.2 --- Recommendation for Future Work --- p.52 / References --- p.53 / Appendix A --- p.54 / Publications and Presentations --- p.54

It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.

Parameter variations, noise susceptibility, and increasing energy dissipation of CMOS devices have been recognized as major challenges in circuit and micro-architecture design in the nanometer regime. Among these, parameter variations and noise susceptibility are increasingly causing CMOS devices to behave in an "unreliable" or "probabilistic" manner. To address these challenges, a shift in design paradigm, from current day deterministic designs to "statistical" or "probabilistic" designs is deemed inevitable. Motivated by these considerations, I introduce and define probabilistic Boolean logic, whose logical operators are by definition "correct" with a probability 1/2 <= p <= 1. While most of the laws of conventional Boolean logic can be naturally extended to be valid in the probabilistic case, there are a few significant departures. We also show that computations realized using implicitly probabilistic Boolean operators are more energy efficient than their counterparts which use explicit sources of randomness, in the context of probabilistic Boolean circuits as well as probabilistic models with state, Rabin automata. To demonstrate the utility of implicitly probabilistic elements, we study a family of probabilistic architectures: the probabilistic system-on-a-chip PSOC, based on CMOS devices rendered probabilistic due to noise, referred to as probabilistic CMOS or PCMOS devices. These architectures yield significant improvements, both in the energy consumed as well as in the performance in the context of probabilistic or randomized applications with broad utility. Finally, we extend the consideration of probability of correctness to arithmetic operations, through probabilistic arithmetic. We show that in the probabilistic context, substantial savings in energy over correct arithmetic operations may be achieved. This is the theoretical basis of the energy savings reported in the video decoding and radar processing applications that has been demonstrated in prior work.

Le futur collisionneur électron-positon ILC est un projet d'envergure internationale. Il doit poursuivre le programme scientifique actuellement en cours auprès du Large Hadron Collider (LHC) lorsque celui-ci aura atteint les limites de sa sensibilité. Cet ambitieux projet d'accélérateur nécessitera également la mise en place de nouveaux concepts du point de vue de la détection. Afin d'optimiser la reconstruction des événements, une approche basée sur le suivit de particule (Particle Flow) a ainsi été adoptée. Jusqu'à aujourd'hui, les calorimètres hadroniques ont souvent représenté le point faible des expériences de physique des hautes énergies auprès de collisionneurs. En effet, leur faible granularité dégrade fortement la résolution en énergie des jets reconstruits. Dans le cas de l'ILC, il est envisagé d'utiliser des calorimètres de forte granularité de manière à distinguer clairement chaque dépôt d'énergie. Il est ainsi possible d'améliorer la résolution en énergie globale de l'expérience en utilisant le détecteur le plus approprié pour caractériser chaque particule fille issue de la collision. Les membres de la collaboration CALICE sont en charge du développement de ces calorimètres ultra granulaires. Dans ce cadre, plusieurs projets de calorimètres sont à l'étude afin de s'assurer que la technologie finalement choisie soit optimale. Durant ces trois dernières années, j'ai participé au développement de l'un de ces détecteurs : le calorimètre hadronique semi digital SDHCAL. Cet instrument utilise des chambres à plaques résistives de verre (GRPC) en tant qu'élément sensible. Ce calorimètre à échantillonnage comporte 48 plans de détection successifs séparés par de l'acier. Il est segmenté latéralement en cellules de un centimètre carré, pour un total de 50 millions de canaux. La dissipation thermique de l'électronique de lecture embarquée est un facteur clef du projet. […] / The future electron-positon linear collider ILC is an international project aiming to follow and go forward the scientific program which is actually on-going at the Large Hadron Collider (LHC). Such a leptonic collider project implies also new concepts in particle detection to ensure a better event reconstruction : this can be achieved by using particle flow techniques. Until now, hadronic calorimeters are the bottleneck of particle detectors concepts. They are usually poorly granular and they contribute strongly to degrade the energy resolution of the reconstructed jets. In the ILC case, we aim to build highly granular calorimeters to distinguish each energy deposit. This way we can improve the energy resolution by using the most suitable detector to perform energy measurement for each particle. The CALICE collaboration federate the highly granular calorimeters R&D activities in order to distinguish the best technology for the final detector concept. I worked for the last three years on one of those projects : the SDHCAL, a semi digital hadronic calorimeter based on glass resistive plate chambers (GRPC). This 48 layer sampling calorimeter is segmented in cells of one square centimeter for a total of 50 millions channels. […]

L’Onera développe des capteurs inertiels MEMS vibrants avec des performances qui peuvent intéresser des applications spatiales. Les électroniques analogiques traditionnellement associées ne sont à priori pas limitantes par rapport aux performances physiques des capteurs. En revanche, elles se montrent encombrantes, non reconfigurables, et ne délivrent pas les grandeurs mesurées sous forme numérique à l’ordinateur de bord. En outre,dans le cadre d’une utilisation spatiale, elles sont sujettes à dépendance et à obsolescence :le remplacement d’un composant implique une nouvelle qualification.Cette thèse propose une nouvelle architecture numérique générique, limitant au maximum les composants analogiques nécessaires. Les travaux portent principalement sur deux capteurs développés par l’Onera : l’accéléromètre à lame vibrante VIA et le gyromètre vibrant à effet Coriolis VIG, mais sont justement transposables à d’autres familles. Une première fonction clé identifiée est la datation d’évènements pour la mesure de fréquence et de phase, une seconde concerne la synthèse numérique directe de fréquence pour le pilotage de résonateurs, et une troisième traite la génération de signaux sinusoïdaux purs à partir des trains binaires délivrés par le système numérique. Ces fonctions sont réalisées sous forme de périphériques numériques autour d’un processeur embarqué, le tout synthétisé sur composant programmable FPGA. Le manuscrit débute par un rappel des lois physiques et des technologies de mesure inertielle, suivi d’une revue des oscillateurs, analogiques et numériques, afin de déterminer l’architecture numérique souhaitée. Le chapitre suivant aborde de façon théorique les fonctions numériques envisagées, et en détermine les éléments de performance. La mise en oeuvre de ces fonctions et les premiers résultats expérimentaux sont ensuite présentés d’abord au niveau de la fonction seule, et enfin dans une architecture complète incluant le capteur et le logiciel embarqué, pour fournir de vraies mesures inertielles. Ces résultats encouragent le déploiement d’électronique numérique dans les prochaines générations de capteurs. / Onera has been developing vibrating inertial MEMS sensors with performances good enough for space uses. Associated conventional analog electronics are not limiting the physical performances of the sensors. They are, however, bulky, not reconfigurable, and do not deliver digital measurements to the on-board computer. Furthermore, when used for space applications, they have to cope with dependency and obsolescence requiring a new qualification when any part is changed.This thesis offers a new digital generic architecture with as few analog parts as possible. Work has been focused on two sensors developed by Onera: the VIA, a vibrating beam accelerometer, and the VIG, a Coriolis vibrating gyro, but can address other sensors. A first digital function identified is event timestamping for frequency and phase measurements; a second key function is the direct digital synthesis of the oscillating sensors driving signal; the third one generates pure sine signals from binary sequences output from the digital platform. These function are implemented as peripherals of an embedded processor on a FPGA.This dissertation firstly reminds physical laws and technologies of inertial measurements, followed by a quick review of oscillators, analog and digital, in order to introduce the chosen digital architecture. A following chapter studies the theory of the digital functions considered and identifies their performances. Afterwards, realisations and first experimental results are exposed, at a function level first, at a global level then, with the sensor and the embedded software to provide real inertial readings. The results gathered boost the idea of deploying digital electronics in future sensor releases.

Les interfaces cerveau-machine (ICM) permettent de contrôler un appareil électronique grâce aux signaux cérébraux. Plusieurs méthodes de mesure de ces signaux, invasives ou non, peuvent être utilisées. L'électro-encéphalographie (EEG) est la méthode non-invasive la plus étudiée car elle propose une bonne résolution temporelle et le matériel nécessaire est bien moins volumineux que les systèmes de mesure des champs magnétiques.L'EEG a cependant une faible résolution spatiale, ce qui limite les performances des ICM utilisant cette méthode de mesure. Ce souci de résolution spatiale peut être réglé en utilisant le problème inverse de l'EEG, qui permet de passer des potentiels mesurés en surface à une distribution volumique des sources de courant dans le cerveau. Le principal verrou de cette technique est le temps nécessaire (plusieurs heures) pour calculer avec une station de travail la matrice permettant de résoudre leproblème inverse. Dans le cadre de cette thèse, nous avons étudié les solutions actuelles pour accélérer matériellement la conception de cette matrice. Nous avons ainsi proposé, conçu et testé une architecture électronique dédiée à ces traitements pour ICM. Les premiers résultats démontrent que notre solution permet de passer de plusieurs heures de calcul sur une station de travail à quelques minutes sur circuit reconfigurable. Cette accélération des traitements d'imagerie par EEG facilitera grandement la recherche sur l'utilisation du problème inverse et ouvrira ainsi de nouvelles perspectives pour le domaine de l'ICM. / Brain-Computer Interfaces (BCI) are systems that use brain activity to control an external device. Various techniques can be used to collect the neural signals. The measurement can be invasive ornon-invasive. Electroencephalography (EEG) is the most studied non-invasive method. Indeed, EEG offers a fine temporal resolution and ease of use but its spatial resolution limits the performances of BCI based on EEG. The spatial resolution of EEG can be improved by solving the EEG inverse problem, which allows to determine the distribution of electrical sources in the brain from EEG. Currently, the main difficulty is the time needed(several hours) to compute the matrix which is used to solve the EEG inverse problem. This document describes the proposed solution to provide a hardware acceleration of the matrix computation. A dedicated electronic architecture has been implemented and tested. First results show that the proposed architecture divides the calculation time by a factor of 60 on a programmable circuit. This acceleration opens up new perspectives for EEG BCI.

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.