This dissertation investigates a methodology that can be used to design and optimize an energy efficient 3D-integrated image sensing and compression system for network based applications. A system level model that evaluates the effect of design choices and external environmental factors to the power/performance of the system is presented. Three design principles are considered in formulating the system model. First, a multi-segment/multi-core image compression approach is presented as a combined solution with 3D-stacking to reduce the workload of the compression module, effectively increasing power efficiency of the system. Second, vertical stacking reduces the rate of heat removal from the compression module and ADC resulting in higher temperature and noise in the photodiode tier. Therefore, due to the die-to-die thermal coupling, image quality is strongly influenced by image throughput, architectural, and external environment factors. Third, heterogeneous integration of the photosensor module and compression engine is presented as a method to increase power efficiency of the system. Scaling the compression engine to deep sub-micron technology provides substantial power and chip area benefits, while CMOS image sensor retains reliability with less advanced 180nm process. The dissertation concludes that 3D heterogeneous integration can increase power/performance efficiency of an image sensor system, but die-to-die thermal coupling may provide challenges in managing the quality of the compressed images.

Το σύστημα που σχεδιάστηκε βασίζεται στον soft-core επεξεργαστή Nios II της ALTERA. Εκτελεί βασικές ρουτίνες επεξεργασίας εικόνας όπως Median Filtering, Negative, Edge Detection, Image Sharpening και ο έλεγχος του επιτυγχάνεται μέσω της οθόνης αφής LTM. Αναλύονται όλες οι βασικές έννοιες, και περιγράφεται τόσο ο επεξεργαστής όσο και οι περιφερειακές μονάδες που χρησιμοποιήθηκαν (LTM, D5M Camera, PIO κτλ.). Το όλο σύστημα υλοποιήθηκε στο DE2-70 Board της ALTERA. / The system that has been developed, is based on the ALTERA‘s soft-core processor Nios II. It implements basic image-processing routines such as Median Filtering, Negative, Edge Detection, Image Sharpening and the control of the system is achieved via the LTM Touch Screen. All fundamental concepts are analyzed, and both the processor and the peripherals used (LTM, D5M Camera, PIO etc) are described in detail. The system was implemented on the ALTERAs DE2-70 Board.

Το σύστημα που σχεδιάστηκε βασίζεται στον soft-core επεξεργαστή Nios II της ALTERA. Εκτελεί βασικές ρουτίνες επεξεργασίας ήχου όπως echo, reverberation, volume leveling, fir filtering και ο έλεγχος του επιτυγχάνεται ασύρματα, μέσω ενός πληκτρολογίου υπερύθρων. Αναλύονται όλες οι βασικές έννοιες, και περιγράφεται τόσο ο επεξεργαστής όσο και οι περιφερειακές μονάδες που χρησιμοποιήθηκαν (VGA, LCD, PIO κτλ.). Το όλο σύστημα υλοποιήθηκε στο DE2 Board της ALTERA. / The system that has been developed, is based on the ALTERA‘s soft-core processor Nios II. It implements basic sound-processing routines such as echo, reverberation, volume leveling, fir filtering and the control of the system is achieved via an infra red keyboard (wireless). All fundamental concepts are analyzed, and both the processor and the peripherals used (VGA, LCD, PIO etc) are described in detail. The system was implemented on the ALTERAs DE2 Board.

The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.

Este trabalho apresenta um sistema de Síntese de Alto Nível — geração automática de uma descrição estrutural no nível RT a partir de uma descrição comportamental algorítmica [MCF 88] —, abordando as tarefas de compilação para representação interna, transformações comportamentais, escalonamento, alocação, mapeamento e gera.são do controle. Sua principal contribuição esta na fase de transformações comportamentais, através da qual é possível explorar globalmente o paralelismo existente na descried° do sistema digital e, de maneira sistemática, pesquisar o espaço de projeto, ou seja, as possíveis implementações para o sistema digital, identificando a que melhor satisfaz as restrições especificadas pelo projetista. A Linguagem de Descried° de Hardware (HDL) usada no sistema de síntese é VHDL que oferece recursos para se descrever comportamento e estrutura, e se especificar restrições de projeto, alem de ter sido adotada como padrão pela IEEE. Parte-se da descried° algorítmica em VHDL comportamental do sistema digital. Tal descrição é compilada para uma representação interna baseada em grafos: cada bloco básico — seqüência de operações sem desvio — e representado por um Grafo de Fluxo de Dados (GFD); a transferência de controle entre blocos básicos — desvios condicionais e incondicionais — é representada pelo Grafo de Fluxo de Controle (GFC); e as relações de hierarquia — entidade, arquitetura, processos, subprogramas — são representadas pelo Grafo de Entidade (GE). O sistema de transformações é tal que a escolha e a ordem da aplicação das transformações possíveis (agrupa blocos consecutivos, agrupa ramos de if, desenrola laços) sobre um GFC gera uma Arvore — a Arvore de Transformações — cujos nodos folha representam os GFD's iniciais e os nodos internos os GFD's obtidos pela transformação aplicada sobre os seus nodos filhos. Construída a Arvore de Transformações, realiza-se um caminhamento em pós-ordem, determinando-se a melhor implementação possível para cada nodo da Arvore de Transformações. Por melhor implementação entenda-se a que, no mínimo, satisfaça as restrições de tempo ou de recursos especificadas pelo projetista. Para cada implementação, obtida usando-se algoritmos de escalonamento, alocação e mapeamento existentes, calcula-se um custo em fungi° dos recursos — unidades funcionais, registradores, interconexões — e do tempo — passos de controle — necessários implementação. Feito isso, caminha-se em pré-ordem pela árvore de Transformações comparando-se o custo da implementação do nodo pai com os custos de implementação dos seus nodos filhos: se o custo dos nodos filhos a maior que o do nodo pai, este é selecionado e seus nodos filhos não são visitados; caso contrario, a transformações que o gerou é descartada e visita-se os nodos filhos. Os nodos selecionados fardo parte da implementação final. O modelo de hardware utilizado adota a divisão clássica de sistema digital em Parte Operativa e Parte de Controle, como apresentada em [DAV 83]. Na implementação do prot6tipo do sistema de síntese escolheu-se, para o escalonamento e a alocação, o algoritmo Force-directed que possui complexidade linear — 0(n2 ) no pior caso — e tem mostrado bons resultados em comparação com os demais existentes [PAU 89]. Para o mapeamento de registradores adotou-se o algoritmo do programa REAL [KUR 87] também de complexidade linear; o mapeamento de unidades funcionais e interconexões baseia-se em [PAN 87]. 0 controlador a obtido diretamente do GFC final: cada nodo representa um estado e as arestas representam as transições entre estados. 0 protótipo foi aplicado a vários exemplos, relatados na literatura, mostrando resultados comparáveis. Aplicando-se o protótipo sobre exemplos com fluxo de controle mais complexo, verifica-se a eficiência do sistema de transformações na exploração do espaço de projeto. / High Level Synthesis is the automatic generation of a structural description of a circuit at the RT level from a behavioral description at the algorithm level [MCF 88]. In this work, a High Level Synthesis System which deals with the tasks of compilation to internal representation, behavioral transformations, scheduling, allocation, mapping and control generation is presented. Its main contribution is the behavioral transformation process. It makes possible the exploration of the global parallelism in the behavioral description and, systematically, to search the design space in order to find the structure that best fits the resource and timing constraints specified by the designer. The Hardware Description Language (HDL) used in the synthesis system is VHDL, HDL standardized by IEEE, which offers facilities for the behavior description, structure description and for the specification of design constraints. The input to the synthesis system is a behavioral algorithmic VHDL description of the digital system under design. This description is translated to an internal representation based on graphs: each basic block (sequence of operations without branches) is represented by a Data Flow Graph (DFG); the transfer of control between basic blocks (conditional and inconditional branches) is represented by a Control Flow Graph (CFG); the hierarchy of description (entity, architectural body, processes, subprograms) is represented by the Entity Graph (EG). The set of behavioral transformations is such that the selection and sequence of applicable transformations (Merge Consecutive Blocks, Merge If Branches, Unroll Loops, etc.) to a CFG can be represented by a tree, called Transformations Tree. In the Transformations Tree, the leaf nodes represent the initial DFGs and the internal nodes represent the DFGs obtained by the transformations applied on its son nodes. After the Transformation Tree has been generated, a transversal post-order is used to determine the best possible implementation for each node of the Transformations Tree. The best possible implementation is the one that, at least, satisfy the timing and resources constraints specified by the designer. A cost is determined in terms of the timing (control steps) and resources (functional units, registers, interconections, etc.) required by each implementation, which is produced using traditional algorithms for scheduling and allocation. Once the implementation for each node is done, a transversal pre-order is used to compare the implementation cost of a node, with the implementation costs of its son nodes: if the cost of its son nodes is greater, the father node is selected and its son nodes are not visited; otherwise the transformation that produced the father node is discarded, and the son nodes are visited. The selected nodes will be in the final implementation. The hardware model used in the synthesis system adopts the classical division of the digital system in a Data-Path and a Controller, such as presented in [DAV 83]. In the implementation of the synthesis system prototype, the Force-Directed algorithm [PAU 89] was adopted for scheduling and allocation, which has linear complexity — in the worst case 0(n2 ) — and produces good results when compared with other algorithms [PAU 91]. The algorithm of the REAL program [KUR 87] was used for the mapping of registers, which also has linear complexity. The mapping of functional units and interconections uses the ideas from [PAN 87]. The controller is directly obtained from the final GFC: each node represents a state and the transitions between states are represented by the edges. The prototype of the synthesis system, which is implemented in C, on SUN workstations, was applied to various examples of the literature and has showed comparable results. When applied to examples with more complex control flow, the efficiency of the set of behavioral transformations in the design space exploration can be verified.

Este trabalho apresenta um sistema de Síntese de Alto Nível — geração automática de uma descrição estrutural no nível RT a partir de uma descrição comportamental algorítmica [MCF 88] —, abordando as tarefas de compilação para representação interna, transformações comportamentais, escalonamento, alocação, mapeamento e gera.são do controle. Sua principal contribuição esta na fase de transformações comportamentais, através da qual é possível explorar globalmente o paralelismo existente na descried° do sistema digital e, de maneira sistemática, pesquisar o espaço de projeto, ou seja, as possíveis implementações para o sistema digital, identificando a que melhor satisfaz as restrições especificadas pelo projetista. A Linguagem de Descried° de Hardware (HDL) usada no sistema de síntese é VHDL que oferece recursos para se descrever comportamento e estrutura, e se especificar restrições de projeto, alem de ter sido adotada como padrão pela IEEE. Parte-se da descried° algorítmica em VHDL comportamental do sistema digital. Tal descrição é compilada para uma representação interna baseada em grafos: cada bloco básico — seqüência de operações sem desvio — e representado por um Grafo de Fluxo de Dados (GFD); a transferência de controle entre blocos básicos — desvios condicionais e incondicionais — é representada pelo Grafo de Fluxo de Controle (GFC); e as relações de hierarquia — entidade, arquitetura, processos, subprogramas — são representadas pelo Grafo de Entidade (GE). O sistema de transformações é tal que a escolha e a ordem da aplicação das transformações possíveis (agrupa blocos consecutivos, agrupa ramos de if, desenrola laços) sobre um GFC gera uma Arvore — a Arvore de Transformações — cujos nodos folha representam os GFD's iniciais e os nodos internos os GFD's obtidos pela transformação aplicada sobre os seus nodos filhos. Construída a Arvore de Transformações, realiza-se um caminhamento em pós-ordem, determinando-se a melhor implementação possível para cada nodo da Arvore de Transformações. Por melhor implementação entenda-se a que, no mínimo, satisfaça as restrições de tempo ou de recursos especificadas pelo projetista. Para cada implementação, obtida usando-se algoritmos de escalonamento, alocação e mapeamento existentes, calcula-se um custo em fungi° dos recursos — unidades funcionais, registradores, interconexões — e do tempo — passos de controle — necessários implementação. Feito isso, caminha-se em pré-ordem pela árvore de Transformações comparando-se o custo da implementação do nodo pai com os custos de implementação dos seus nodos filhos: se o custo dos nodos filhos a maior que o do nodo pai, este é selecionado e seus nodos filhos não são visitados; caso contrario, a transformações que o gerou é descartada e visita-se os nodos filhos. Os nodos selecionados fardo parte da implementação final. O modelo de hardware utilizado adota a divisão clássica de sistema digital em Parte Operativa e Parte de Controle, como apresentada em [DAV 83]. Na implementação do prot6tipo do sistema de síntese escolheu-se, para o escalonamento e a alocação, o algoritmo Force-directed que possui complexidade linear — 0(n2 ) no pior caso — e tem mostrado bons resultados em comparação com os demais existentes [PAU 89]. Para o mapeamento de registradores adotou-se o algoritmo do programa REAL [KUR 87] também de complexidade linear; o mapeamento de unidades funcionais e interconexões baseia-se em [PAN 87]. 0 controlador a obtido diretamente do GFC final: cada nodo representa um estado e as arestas representam as transições entre estados. 0 protótipo foi aplicado a vários exemplos, relatados na literatura, mostrando resultados comparáveis. Aplicando-se o protótipo sobre exemplos com fluxo de controle mais complexo, verifica-se a eficiência do sistema de transformações na exploração do espaço de projeto. / High Level Synthesis is the automatic generation of a structural description of a circuit at the RT level from a behavioral description at the algorithm level [MCF 88]. In this work, a High Level Synthesis System which deals with the tasks of compilation to internal representation, behavioral transformations, scheduling, allocation, mapping and control generation is presented. Its main contribution is the behavioral transformation process. It makes possible the exploration of the global parallelism in the behavioral description and, systematically, to search the design space in order to find the structure that best fits the resource and timing constraints specified by the designer. The Hardware Description Language (HDL) used in the synthesis system is VHDL, HDL standardized by IEEE, which offers facilities for the behavior description, structure description and for the specification of design constraints. The input to the synthesis system is a behavioral algorithmic VHDL description of the digital system under design. This description is translated to an internal representation based on graphs: each basic block (sequence of operations without branches) is represented by a Data Flow Graph (DFG); the transfer of control between basic blocks (conditional and inconditional branches) is represented by a Control Flow Graph (CFG); the hierarchy of description (entity, architectural body, processes, subprograms) is represented by the Entity Graph (EG). The set of behavioral transformations is such that the selection and sequence of applicable transformations (Merge Consecutive Blocks, Merge If Branches, Unroll Loops, etc.) to a CFG can be represented by a tree, called Transformations Tree. In the Transformations Tree, the leaf nodes represent the initial DFGs and the internal nodes represent the DFGs obtained by the transformations applied on its son nodes. After the Transformation Tree has been generated, a transversal post-order is used to determine the best possible implementation for each node of the Transformations Tree. The best possible implementation is the one that, at least, satisfy the timing and resources constraints specified by the designer. A cost is determined in terms of the timing (control steps) and resources (functional units, registers, interconections, etc.) required by each implementation, which is produced using traditional algorithms for scheduling and allocation. Once the implementation for each node is done, a transversal pre-order is used to compare the implementation cost of a node, with the implementation costs of its son nodes: if the cost of its son nodes is greater, the father node is selected and its son nodes are not visited; otherwise the transformation that produced the father node is discarded, and the son nodes are visited. The selected nodes will be in the final implementation. The hardware model used in the synthesis system adopts the classical division of the digital system in a Data-Path and a Controller, such as presented in [DAV 83]. In the implementation of the synthesis system prototype, the Force-Directed algorithm [PAU 89] was adopted for scheduling and allocation, which has linear complexity — in the worst case 0(n2 ) — and produces good results when compared with other algorithms [PAU 91]. The algorithm of the REAL program [KUR 87] was used for the mapping of registers, which also has linear complexity. The mapping of functional units and interconections uses the ideas from [PAN 87]. The controller is directly obtained from the final GFC: each node represents a state and the transitions between states are represented by the edges. The prototype of the synthesis system, which is implemented in C, on SUN workstations, was applied to various examples of the literature and has showed comparable results. When applied to examples with more complex control flow, the efficiency of the set of behavioral transformations in the design space exploration can be verified.

Este trabalho apresenta um sistema de Síntese de Alto Nível — geração automática de uma descrição estrutural no nível RT a partir de uma descrição comportamental algorítmica [MCF 88] —, abordando as tarefas de compilação para representação interna, transformações comportamentais, escalonamento, alocação, mapeamento e gera.são do controle. Sua principal contribuição esta na fase de transformações comportamentais, através da qual é possível explorar globalmente o paralelismo existente na descried° do sistema digital e, de maneira sistemática, pesquisar o espaço de projeto, ou seja, as possíveis implementações para o sistema digital, identificando a que melhor satisfaz as restrições especificadas pelo projetista. A Linguagem de Descried° de Hardware (HDL) usada no sistema de síntese é VHDL que oferece recursos para se descrever comportamento e estrutura, e se especificar restrições de projeto, alem de ter sido adotada como padrão pela IEEE. Parte-se da descried° algorítmica em VHDL comportamental do sistema digital. Tal descrição é compilada para uma representação interna baseada em grafos: cada bloco básico — seqüência de operações sem desvio — e representado por um Grafo de Fluxo de Dados (GFD); a transferência de controle entre blocos básicos — desvios condicionais e incondicionais — é representada pelo Grafo de Fluxo de Controle (GFC); e as relações de hierarquia — entidade, arquitetura, processos, subprogramas — são representadas pelo Grafo de Entidade (GE). O sistema de transformações é tal que a escolha e a ordem da aplicação das transformações possíveis (agrupa blocos consecutivos, agrupa ramos de if, desenrola laços) sobre um GFC gera uma Arvore — a Arvore de Transformações — cujos nodos folha representam os GFD's iniciais e os nodos internos os GFD's obtidos pela transformação aplicada sobre os seus nodos filhos. Construída a Arvore de Transformações, realiza-se um caminhamento em pós-ordem, determinando-se a melhor implementação possível para cada nodo da Arvore de Transformações. Por melhor implementação entenda-se a que, no mínimo, satisfaça as restrições de tempo ou de recursos especificadas pelo projetista. Para cada implementação, obtida usando-se algoritmos de escalonamento, alocação e mapeamento existentes, calcula-se um custo em fungi° dos recursos — unidades funcionais, registradores, interconexões — e do tempo — passos de controle — necessários implementação. Feito isso, caminha-se em pré-ordem pela árvore de Transformações comparando-se o custo da implementação do nodo pai com os custos de implementação dos seus nodos filhos: se o custo dos nodos filhos a maior que o do nodo pai, este é selecionado e seus nodos filhos não são visitados; caso contrario, a transformações que o gerou é descartada e visita-se os nodos filhos. Os nodos selecionados fardo parte da implementação final. O modelo de hardware utilizado adota a divisão clássica de sistema digital em Parte Operativa e Parte de Controle, como apresentada em [DAV 83]. Na implementação do prot6tipo do sistema de síntese escolheu-se, para o escalonamento e a alocação, o algoritmo Force-directed que possui complexidade linear — 0(n2 ) no pior caso — e tem mostrado bons resultados em comparação com os demais existentes [PAU 89]. Para o mapeamento de registradores adotou-se o algoritmo do programa REAL [KUR 87] também de complexidade linear; o mapeamento de unidades funcionais e interconexões baseia-se em [PAN 87]. 0 controlador a obtido diretamente do GFC final: cada nodo representa um estado e as arestas representam as transições entre estados. 0 protótipo foi aplicado a vários exemplos, relatados na literatura, mostrando resultados comparáveis. Aplicando-se o protótipo sobre exemplos com fluxo de controle mais complexo, verifica-se a eficiência do sistema de transformações na exploração do espaço de projeto. / High Level Synthesis is the automatic generation of a structural description of a circuit at the RT level from a behavioral description at the algorithm level [MCF 88]. In this work, a High Level Synthesis System which deals with the tasks of compilation to internal representation, behavioral transformations, scheduling, allocation, mapping and control generation is presented. Its main contribution is the behavioral transformation process. It makes possible the exploration of the global parallelism in the behavioral description and, systematically, to search the design space in order to find the structure that best fits the resource and timing constraints specified by the designer. The Hardware Description Language (HDL) used in the synthesis system is VHDL, HDL standardized by IEEE, which offers facilities for the behavior description, structure description and for the specification of design constraints. The input to the synthesis system is a behavioral algorithmic VHDL description of the digital system under design. This description is translated to an internal representation based on graphs: each basic block (sequence of operations without branches) is represented by a Data Flow Graph (DFG); the transfer of control between basic blocks (conditional and inconditional branches) is represented by a Control Flow Graph (CFG); the hierarchy of description (entity, architectural body, processes, subprograms) is represented by the Entity Graph (EG). The set of behavioral transformations is such that the selection and sequence of applicable transformations (Merge Consecutive Blocks, Merge If Branches, Unroll Loops, etc.) to a CFG can be represented by a tree, called Transformations Tree. In the Transformations Tree, the leaf nodes represent the initial DFGs and the internal nodes represent the DFGs obtained by the transformations applied on its son nodes. After the Transformation Tree has been generated, a transversal post-order is used to determine the best possible implementation for each node of the Transformations Tree. The best possible implementation is the one that, at least, satisfy the timing and resources constraints specified by the designer. A cost is determined in terms of the timing (control steps) and resources (functional units, registers, interconections, etc.) required by each implementation, which is produced using traditional algorithms for scheduling and allocation. Once the implementation for each node is done, a transversal pre-order is used to compare the implementation cost of a node, with the implementation costs of its son nodes: if the cost of its son nodes is greater, the father node is selected and its son nodes are not visited; otherwise the transformation that produced the father node is discarded, and the son nodes are visited. The selected nodes will be in the final implementation. The hardware model used in the synthesis system adopts the classical division of the digital system in a Data-Path and a Controller, such as presented in [DAV 83]. In the implementation of the synthesis system prototype, the Force-Directed algorithm [PAU 89] was adopted for scheduling and allocation, which has linear complexity — in the worst case 0(n2 ) — and produces good results when compared with other algorithms [PAU 91]. The algorithm of the REAL program [KUR 87] was used for the mapping of registers, which also has linear complexity. The mapping of functional units and interconections uses the ideas from [PAN 87]. The controller is directly obtained from the final GFC: each node represents a state and the transitions between states are represented by the edges. The prototype of the synthesis system, which is implemented in C, on SUN workstations, was applied to various examples of the literature and has showed comparable results. When applied to examples with more complex control flow, the efficiency of the set of behavioral transformations in the design space exploration can be verified.

The transistor count for todays VLSI technology reaches 40 million transistors on one chip. In order to successfully design a system with such complexity, new computer-aided design (CAD) tools are needed. This dissertation shows approaches for coping with the problem of increasing complexity of VLSI design in three aspects: 1) capturing a higher level of abstraction, 2) using a new target architecture, and 3) using a new optimization technique. The advantage of working at a higher level of abstraction is that the number of objects that designers have to manipulate is reduced so that more complex systems can be delivered in shorter periods of time. The functions that can be used to capture higher levels of abstraction are surveyed and categorized into an is-a hierarchy. A partitioned-bus architecture that consists of complex functional units used to realize complex functions is proposed. The issues of synthesizing the complex functions to the partitioned-bus architecture are addressed. These issues are focused on the functional partitioning problem which is a known NP-complete problem. Algorithms used to optimize several metrics that affect the solution qualities of functional partitioning are presented. The metrics include communication buffer size, register file size, system delay, the number of buses, the number of links, and the number of multiplexers. These metrics are used to form a cost function, which is utilized by the Problem Space Genetic Partitioning algorithm (PSGP) to search for a good solution. Test cases with known optimal solutions are used to evaluate the solution qualities that PSGP can attain under run time and memory space constraints. The experimental results show that PSGP can reach an average about 87% of the optima for two-way partitioning. Another study also shows that PSGP outperforms the widely used Simulated Annealing algorithm. / Ph. D.

This thesis provides a thorough analysis of the theoretical foundations and properties of the Spectral Warping Transform. The spectral warping transform is defined as a time-domain-to-time-domain digital signal processing transform that shifts the frequency components of a signal along the frequency axis. The z -transform coefficients of a warped signal correspond to z -domain ‘samples’ of the original signal that are unevenly spaced along the unit circle (equivalently, frequency-domain coefficients of the warped signal correspond to frequency-domain samples of the original signal that are unevenly spaced along the frequency axis). The location of these unevenly spaced frequency-domain samples is determined by a z -domain mapping function. This function may be arbitrary, except that it must map the unit circle to the unit circle. It is shown that, in addition to the frequency location, the bandwidth, duration and amplitude of each frequency component of a signal are affected by spectral warping. Specifically, frequency components within bands that are expanded in frequency have shortened durations and larger amplitudes (conversely, components in compressed frequency bands become longer with smaller amplitudes). A property related to the expansion and compression of the duration of frequency components is that if a signal is time delayed (its digital sequence is prepended with zeroes) then each of the frequency components will have a different delay after warping. This time-domain separation phenomenon is useful for separating in time the frequency components of a signal. Such separation is employed in the generation of spectrally flat chirp signals. Because spectral warping will generally expand the duration of some frequency components within a signal, the transform must produce more output samples than there are (non-zero) input samples in order to avoid time-domain aliasing. A discussion of the necessary output signal length is presented. Particular attention is given to spectral warping using all-pass mapping function, which can be realised as a cascade of all-pass filters. There exists an efficient hardware implementation for this all-pass SW realisation [1, 2]. A proof-of-concept application-specific integrated circuit that performs the core operations required by this algorithm was developed. Another focus of the presented research is spectral warping using a piecewise- linear mapping function. This type of spectral warping has the advantage that the changes in frequency, duration and amplitude between the non-warped and warped signals are constant factors over fixed frequency bands. A matrix formulation of the spectral warping transformation is developed. It presents the spectral warping transform as a single matrix multiplication. The transform matrix is the product of the three matrices that represent three conceptual steps. The first step is to apply a discrete Fourier transform to the time-domain signal, providing the frequency-domain representation. Step two is an interpolation to produce the signal content at the desired new frequency samples. This interpolation effectively provides the frequency warping. The final step is an inverse DFT to transform the signal back into the time domain. A special case of the spectral warping transform matrix has the same result as a linear (finite-impulse-response) filter, showing that spectral warping is a generalisation of linear filtering. The conditions for the invertibility of the spectral warping transformation are derived. Several possible realisation of the SW transform are discussed. These include two realisation using parallel finite-impulse-response filter banks and a realisation that uses a cascade of infinite-impulse-response filters. Finally, examples of applications for the spectral warping transform are given. These include: non-uniform spectral analysis (and signal generation), approximate spectral analysis in the time domain, and filter design. This thesis concludes that the SW transform is a useful tool for the manipulation of the frequency content of digital signals, and is particularly useful when the frequency content of a signal (or the frequency response of a system) over a limited band is of interest. It is also claimed that the SW transform may have valuable applications for embedded mixed-signal testing.

e-Government systems are considered by both governments and international organisations to improve administration and management. In Tanzania, an e-government system for education administration, EMIS, is partly implemented but shows several limitations. Statistical data is collected but the process is resource demanding and much of the collected data are never put into the system, and therefore remain inaccessible from this electronic system. The overall aim of this study is to propose an approach to designing more efficient e-government systems within the education sector. The focus is on public schools. The more specific aim of the present study is to: explore more efficient data transfer (faster, more reliable, and potentially less resource demanding) by using mobile telephone technology, especially SMS, as a means for statistical data collection for Tanzanian education management. The study is guided by an overall research approach that comprises systems theory and a socio-technical view. This research is performed as a case study, inspired by the ethnographic method and comprises field studies in East Africa. A multi-technique approach is used for empirical data gathering, including literature study, interviews, and direct observations. The analytical process is performed by developing and applying three analytical models: XIF - the eXtended Sustainable ICT Framework   Triple A - Access, Attitude, Awareness Seven Aspects – an Approach Towards Success The contributions of this thesis are as follows. A mobile supported SMS-based statistical data collection process employing a blended digital solution is proposed. Likely effects of such a system would be ‘better’ data e.g. less transmission errors, which provides for ‘better’ administration, ‘better’ decision-making, and also provides for transparency. Moreover, it is very likely that the proposed system is significantly less resource demanding than the present system. The three analytical models that are developed specifically for this study have generic characters and can be used during the implementation process of other e-government solutions.  The most important part of the contribution is not the technological solution per se; it is the process that foregoes the actual implementation. The proposal departs specifically from the Tanzanian educational context but has implications for e-government systems solutions and information systems implementation in developing countries in general. Finally, three overall reflections are made based on the major observations of the research findings: the Double ‘e’ Dilemma, on the problem of prioritising electronics before electricity, the Mobiles to Avoid Mobility paradox, highlighting connectivity before mobility, and the opportunity to use the SMS to Combat Corruption weapon.