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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / With the increased concerns for reducing cost and improving reliability in today's telemetry systems, many users are employing simulation and automation to guarantee reliable telemetry systems operation. Pre-Mission simulation of the telemetry system will reduce the cost associated with a loss of mission data. In order to guarantee the integrity of the receive system, the user must be able to simulate several conditions of the transmitted signal. These include Doppler shift and dynamic fade simulation. Additionally, the simulator should be capable of transmitting industry standard PCM data streams to allow pre-mission bit error rate testing of the receive system. Furthermore, the simulator should provide sufficient output power to allow use as a boresite transmitter to check all aspects of the receive link. Finally, the simulator must be able to operate at several frequency bands and modulation modes to keep cost to a minimum.

Thesis (PhD)--University of Stellenbosch, 2005. / ENGLISH ABSTRACT: Keywords: software-defined radio, SDR, quadrature mixing, quadrature modulation, quadrature demodulation, digital compensation, software radio, direct-digital synthesis, DDS. An often-stated goal of software-defined transceiver systems is to perform digital signal conversion as close to the antenna as possible by using high-rate converters. In this dissertation, alternative design principles are proposed, and it is shown that the signal processing techniques based on these principles improve on the prior system's accuracy, while maintaining system flexibility. Firstly, it is proposed that digital compensation can be used to reverse the effects of hardware inaccuracies in the RF front-end of a software-defined radio. Novel compensation techniques are introduced that suppress the signal artefacts introduced by typical frontend hardware. The extent to which such artefacts may be suppressed, is only limited by the accuracy by which they may be measured and digitally represented. A general compensation principle is laid down, which formalises the conditions under which optimal compensation may be achieved. Secondly, it is proposed that, in the design of such RF front-ends, a clear distinction should be drawn between signal processing complexity and frequency translation. It is demonstrated that conventional SDR systems often neglect this principle. As an alternative, quadrature mixing is shown to provide a clear separation between the frequency translation and signal processing problems. However, effective use of quadrature mixing as design approach necessitates the use of accurate compensation techniques to circumvent the hardware inaccuracies typically found in such mixers. Quadrature mixers are proposed as general-purpose front-ends for software-defined radios, and quadrature modulation and demodulation techniques are presented as alternatives to existing schemes. The inherent hardware inaccuracies are analysed and simulated, and appropriate compensation techniques are derived and tested. Finally, the theory is verified with a prototype system. / AFRIKAANSE OPSOMMING: Sleutelwoorde: sagteware-gedefinieerde radio, SDR, haaksfasige menging, haaksfasige modulasie, haaksfasige demodulasie, digitale kompensasie, sagteware-radio, direk-digitale sintese, DDS. 'n Gewilde stelling is dat digitale seinomsetting in sagteware-gedefinieerde kommunikasiestelsels so na as moontlik aan die antenna moet geskied deur gebruik te maak van hoëspoed omsetters. Hierdie verhandeling stel alternatiewe ontwerpsbeginsels voor, en toon aan dat hierdie beginsels die eersgenoemde stelsel se akkuraatheid verbeter, terwyl stelselbuigsaamheid gehandhaaf word. Dit word eerstens voorgestel dat digitale kompensasie gebruik word om die effekte van hardeware-onakkuraathede in die RF-koppelvlak van sagteware-gedefinieerde radio's om te keer. Nuwe kompensasietegnieke, wat seinartefakte weens koppelvlak-onakkuraathede kan onderdruk, word aangebied. Die mate waartoe hierdie artefakte onderdruk kan word, word slegs beperk deur die akkuraatheid waarmee dit gemeet en digitaal voorgestel kan word. 'n Algemene kompensasiebeginsel word neergelê waarin die voorwaardes vir optimale kompensasie vasgelê word. Tweedens word voorgestel dat 'n duidelike onderskeid getref word tussen seinverwerkingskompleksiteit en seinverskuiwing in RF-koppelvlakke. Daar word getoon dat konvensionele SDR-stelsels dikwels nie hierdie beginsel handhaaf nie. 'n Alternatief, naamlik haaksfasige menging, word voorgehou as 'n tegniek wat duidelik onderskei tussen seinverskuiwing en seinverwerking. Akkurate kompensasietegnieke is egter nodig om effektief van sulke mengers gebruik te maak. Haaksfasige mengers word voorgestel as veeldoelige koppelvlakke vir sagteware-gedefinieerde radio's, en haaksfasige modulasie- en demodulasietegnieke word voorgestel as plaasvervangers vir bestaande tegnieke. Die inherente hardeware-onakkuraathede word geanaliseer en gesimuleer, en geskikte kompensasietegnieke word afgelei en getoets. Laastens word die teoretiese resultate met 'n praktiese prototipe bevestig.

<p>Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products.</p><p>Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation.</p><p>The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics.</p><p>The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality.</p><p>In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.</p>

Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products. Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation. The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics. The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality. In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

Dissertation (Ph.D.)--Auburn University,2006. / Abstract. Vita. Includes bibliographic references (p.110-113).

Στα πλαίσια αυτής της διπλωματικής εργασίας μελετήθηκε η θεωρία των Direct Digital Synthesizers, ενώ σχεδιάστηκε και υλοποιήθηκε ένας Dual Direct Digital Synthesizer. Στο πρώτο κεφάλαιο αναφερόμαστε με συντομία στην ιστορική εξέλιξη, στα πλεονεκτήματα και τις εφαρμογές της τεχνολογίας DDS. Στο δεύτερο κεφάλαιο αναλύουμε τον τρόπο λειτουργίας ενός συνθέτη DDS και στην συνέχεια δίνουμε έμφαση, στα λειτουργικά μπλόκ που τον αποτελούν και στο μοντέλο θορύβου του. Στην συνέχεια αναφέρουμε το πρωτόκολλο επικοινωνίας του Dual Synthesizer με τον υπολογιστή καθώς ο έλεγχος πραγματοποιείται απο PC. Η ιδέα αυτή αποτελεί μέρος, ενός μεγαλύτερου σχεδιόυ που διεξάγεται στο Εργαστήριο Ηλεκτρονικών Εφαρμογών του τμήματος Ηλεκτρολόγων Μηχανικών του Πανεπιστημίου Πατρών. Στόχος της ιδέας αυτής είναι η δημιουργία ενος Εργαστηρίου Ηλεκτρονικών Οργάνων (Desktop Lab) το οποίο αφενός δεν θα υστερεί σε τίποτα απο τα συνηθισμένα εργαστήρια αφετέρου ο οποιοσδήποτε θα μπορεί να έχει πρόσβαση σε αυτό μέσω διαδικτύου. Στο τέταρτο κεφάλαιο γίνεται αναφορά του σχεδιασμού του Hardware της γεννήτριας, ενώ στο πέμπτο επικεντρονόμαστε στον προγραμματισμό του FPGA του συστήματος. Στο έκτο κεφάλαιο αναλύεται το software του Dual Synthesizer. Τέλος στο έβδομο κεφάλαιο παραθέτουμε μερικές μετρήσεις που επιβεβαιώνουν την ορθότητα της σχεδίασης και της κατασκευής. / Throughout this dissertation the theody of Direcl Digital Synthesizers was studied while at the same time a Dual Direct Digital Synthesizer was designed and implemented. In the first part we briefly mentioned the evolution, the advantages and some applications of DDS technology. In the second part we analyzed the method of operation of DDS synthesizer and followed up by placing emphasis on the operational blocks which it consists of, and the noise model. After which we noted the communication protocol of the Dual Synthesizer with the computer since it tis controlled by it. This concept is part of a greater ongoing plan in the applied Electronics Laboratory of the department of Electrical Engineering of Upatras. The goal of this idea is the development of an electronic instrument laboratory which would not only have everything a conventional laboratory would have but also could be accessed through the internet. In the fourth part we noted the design of the hardware while in the fifth part, we focused on the programming of the FPGA of the system. In the sixth part we analyzed the software of the Dual Synthesizer. Finally in the seventh part we depicted some measurements that validate the accuracy of the design and implementation.

Thesis--Auburn University, 2006. / Abstract. Includes bibliographic references (p.78-80).

The aim of this thesis is introduce readers to the basics of digital frequency synthesis and design of direct digital synthesizer with circuit AD9951 by Analog Devices. The device will be controlled from a PC via RS232. The device will work with internal oscillator, with the ability to connect an external frequency standard.