Using the vapor-liquid-solid (VLS) growth method, silicon nanowires and germanium nanowires are grown. We find the high growth rate is responsible for the silicon nanowires with less growth defects when they are grown by use of silicon tetrachloride as a precursor and hydrogen as a carrier gas. Based on this funding, large area, high aspect ratio, h111i oriented silicon nanowires are successfully grown on Si (111) and Si (100). Novel growth mechanisms of VLS growth method were discovered in SiOx nanoflowers and silicon nanocones. In SiOx nanoflowers grown at the tip of silicon nanowires, it is found that they are produced via the enhanced oxidation of silicon at the gold-silicon interface. Furthermore, the analysis of the flower pattern reveals that it is the observation of the dense branching morphology on nanoscale and on spherical geometry. For the silicon nanocones, they are grown by the in situ etching of the catalysts of Ga/Al by HCl during the growth. Scanning electron microscopy (SEM), transmission electron microscopy (TEM) reveal that the nanocones are composed of amorphous silicon oxides and crystalline Si. Based on the similar chemistry of hydrogen reduction of SiCl₄ for the growth of silicon nanowires, single crystalline germanium nanowires are grown by use of GeCl4 as a precursor and H₂ as a carrier gas. As one of important application of one dimensional nanostructures, the field emission properties of 1-D nanostructures are explored. The field emission properties of a single graphite nanocone are measured in SEM. The inter-electrode separation is controlled using scanning tunneling microscopy (STM) approach method, allowing the precise and ne determination of the separation. Its Fowler-Nordheim plot shows it emits currents in accordance with the Fowler-Nordheim field emission. Its onset voltage, field enhancement factor show that its basic field emission parameters are comparable to those of a single carbon nanotube. It is observed that single nanocone is damaged after emitting a current of about 100 nA, which seems to be due to its hollow interior structure. / text

Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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