Biosensors are today important devices within various application areas. In this thesis a new type of label-free biosensor device is studied, which is fabricated using the same processes used for the fabrication of integrated circuits. This enables tighter integration and further sensors/biosensor miniaturization. The device is a so-called Thin Film Bulk Acoustic Resonator (FBAR). Within this thesis a low temperature reactive sputtering process for growing AlN thin films with a c-axis inclination of 20-30o has been developed. This enables shear mode FBAR fabrication suitable for in-liquid operation, essential for biosensor applications. Shear mode FBARs were fabricated operating at frequencies above 1GHz exhibiting Q values of 100-200 in water and electromechanical coupling factors kt2 of about 1.8%. This made it possible to move the thickness excited shear mode sensing of biological layers into a new sensing regime using substantially higher operation frequencies than the conventionally used quartz crystal microbalance (QCM) operating at 5-20MHz. Measured noise levels of shear mode FBARs in contact with water showed the resolution to be in the range 0.3ng/cm2 to 7.5ng/cm2. This demonstrated the FBAR resolution without any averaging or additional stabilization measures already to be in the same range as the conventional QCM (5ng/cm2), suggesting that FBARs may be a competitive and low cost alternative to QCM. The linear thickness limit for sensing of biomolecular layers was concluded to be larger than the thickness of the majority of the molecular systems envisaged for FBAR biosensor applications. A temperature compensated shear mode FBAR composite structure was demonstrated with retained coupling factor and Q-value by utilizing the second mode of operation. Understanding has been gained on the sensor operation as well as on how the design parameters influence its performance. Specifically, sensitivity amplification utilizing low acoustic impedance layers in the FBAR structure has been demonstrated and explained. Further, temperature compensated Lamb mode (FPAR) devices were also studied and demonstrated with optimized electromechanical couplings. / wisenet

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance. Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components. / Electronics design division / Sensible Things that Communicate

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Eskilstuna Elektronikpartner (EEPAB) är ett elektronikföretag som tillverkar vinkelgivare till bland annat kranar som är monterade på lastbilsflak. För att EEPAB på ett intressant sätt ska kunna demonstrera sin produkt på mässor har en demonstrator tagits fram. Denna demonstrator består av en fjärrstyrd grävmaskin och en elektronikenhet, som hanterar den analoga signalen från vinkelgivaren. Resultatet, som är vinkelgivarens lutning i grader, presenteras på två sjusegmentdisplayer som är placerade på grävmaskinens bägge sidor. Vinkeln skickas även trådlöst från elektronikenheten, via Bluetooth, till en PC. Grävmaskinens batteri (7,2V) strömförsörjer all hårdvara, vilket gör att demonstratorn är helt portabel. Denna rapport beskriver block för block de olika programfunktioner samt hårdvara, som behövs till en färdig och fungerande demonstrator. / Eskilstuna Elektronikpartner (EEPAB) is an electronics company located in Eskilstuna that produces angle sensors to, for instance, cranes mounted on truck beds. For EEPAB to be able to demonstrate their product on fairs in an interesting way, a demonstrator has been made. The demonstrator consists of a remote controlled excavator and an electronic unit which handles the analog signal from the sensor. The result, which is the angle of the sensor in degrees, is presented on two sevensegment displays that are placed on both sides of the excavator. The angle is also sent wirelessly from the electronic unit via Bluetooth to a PC. The battery of the excavator powers all of the hardware, making the demonstrator fully portable. This thesis report describes the various programfunctions and hardware, part by part, necessary for a complete and functioning demonstrator.

En RMRC, Rail Mounted Railway Crane, är en kran för hantering av containertrafik till och från järnvägsvagnar. Kranen som är helt manuellt styrd utrustas med en semiautomatik som hjälper operatören att positionera kranen. Målpositionen för containern kommer från terminalens logistiksystem. För positioneringen har en lämplig regulator tagits fram som tar hänsyn till den mekaniska påverkan på motorer och växellådor som finns vid acceleration och retardation. Regulatorn har tagits fram och testats i en simuleringsmiljö. Den har sedan implementerats i ett PLC-system och provkörts i labmiljö med PLC och motorer. Regulatorn har förbättrad prestanda jämfört med den regulator som tidigare använts för andra typer av kranar. Den är också lättare att trimma in vid idriftsättning.För positionsåterföringen på de tre rörelserna lyft, tralla och kranåk, har olika typer av givare undersökts och rekommenderat.

The work presented in this paper is about the development of a collision avoidance systemfor a mobile telepresence robot developed by the company Gira technologies AB.The robot is designed to extend the length of time elderly can stay in their homes beforerequiring full-time staed care. The collision avoidance system is needed to help the userto avoid running in to objects or down a stairway. The design must be capable of beingimplemented at low cost, and should not look overtly "robotic" as this would not resultin an appealing industrial design. Herein, dierent techniques are presented and analyzed to nd the best suitable solutionfor the robot. In particular a lot of work is done in taking measurements to nd theright characteristics for the sensors according dierent mounting angles, dierent objectsand distances. A solution is chosen and calculations are made to nd the best positionsto place the sensors to get the best results. A complete solution is presented and implemented in the current system and testedto work as expected.

The task for this thesis was to develop, construct and evaluate a multi‐bus communication system,connected to a PC via USB and capable of communicating in CAN, I2C and SPI and develop drivers for itin National Instruments LabVIEW.In the beginning a study was made of the communication buses followed by an investigation of whattype of hardware that could accomplish this task. A microcontroller unit was selected andprogrammed in MikroElektronika MikroC Pro v.3.2 to act as the interface between the communicationbusses and PC. A PCB prototype of the system was constructed by using Eagle Cad software v.5.6.0. General drivers for this system where created in LabVIEW v.8.6.1 so the end‐user simply can createtheir own applications and control the compatible hardware depending on their type of purposes. Thesystem was tested on criteria’s such as: speed, power consumption, burst performance andtransmission length depending on which communication bus was used.

Using Wireless Sensor Networks (WSNs) in health care system has yielded a tremendous effort in recent years. However, in most of these researches tasks like sensor data processing, health states decision making and emergency messages sending are done by a remote server. Numbers of patient with large scale of sensor data consume a lot of communication resource, bring a burden to the remote server and delay the decision time and notification time. In this paper, we present a prototype of a smart gateway that we have implemented. This gateway is an interconnection and services management platform especially for WSN health care systems at home environments, by building a bridge between WSN and public communication networks, compatible with an on-board data decision system (DDS) and a lightweight database, which enable to make the patient’s health states decision in the gateway in order to get faster response time to the emergencies. We have also designed the communication protocols between WSN, gateway and remote servers. Additionally Ethernet, Wi-Fi and GSM/GPRS communication module are integrated into the smart gateway in order to report and notify information to care-givers.  We have conducted experiments on the proposed smart gateway by performing it together with a wireless home e-health care sensor network. The results show that it is reliable and has low latency and low power consumption.

In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.  The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed. This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer. / I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA. Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls. Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.