<p>The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards.</p><p>Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.</p>

<p>Radio Astronomers demand for highly sensitive astronomical facility. Their demand is a radio telescope that can detect the weakest and deepest radio signal. To fulfill the demand of high sensitive telescope, an entirely new way of realizing a radio telescope is required. One of the most important components in the RF front end that determines the sensitivity of a radio telescope is the Low Noise Amplifier (LNA).</p><p>The project has the selected process technologies which was searched and about the different noise matching topologies, input matching topology, wide band noise and input matching topologies has discussed by the author to the requirement of LNA in Astronomical purposes.</p><p>In this report, the best process technology candidate was chosen apart from selected technology candidates to obtain the minimum noise temperature over broad range frequency upon the modern era of Astronomical LNAs.</p><p>The work was continued to design a single ended LNA to obtain desired transistor parameters while using different noise matching topologies, input matching topologies, wideband noise and input matching topologies to have an LNA achievement with the design goal.</p><p>Further two stage amplifier was implemented to obtain minimum noise temperature, good stability, high gain, good input and output reflection coefficient with less power consumption.</p>

No description available.

No description available.

<p>In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.</p><p> The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.</p><p>This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.</p> / <p>I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.</p><p>Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.</p><p>Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.</p>

<p>In this thesis measurement systems for the purpose of characterization of radio frequency power amplifiers are studied. Methods to increase the speed, accuracy, bandwidth, as well as to reduce the sampling requirements and testing cost are presented. A method intended for signal shaping with respect to peak to-average ratio reduction and its effects-improvements on the radio frequency front-end performance is investigated.</p><p>A time domain measurement system intended for fast and accurate measurements and characterization of radio frequency power amplifiers is discussed. An automated, fast and accurate technique for power and frequency sweep measurements is presented. Multidimensional representation of measured figure of merits is evaluated for its importance on the production-testing phase of power amplifiers.</p><p>A technique to extend the digital bandwidth of a measurement system is discussed. It is based on the Zhu-Frank generalized sampling theorem which decreases the requirements on the sampling rate of the measurement system. Its application for power amplifiers behavioral modeling is discussed and evaluated experimentally.</p><p>A general method for designing multitone for the purpose of out-of-band characterization of nonlinear radio frequency modules using harmonic sampling is presented. It has an application with the validation of power amplifiers behavioral models in their out-of-band frequency spectral support when extracted from undersampled data.</p><p>A method for unfolding the frequency spectrum of undersampled wideband signals is presented. It is of high relevance to state-of-the-art radio frequency measurement systems which capture repetitive waveform based on a sampling rate that violates the Nyquist constraint. The method is presented in a compact form, it eliminates ambiguities caused by folded frequency spectra standing outside the Nyquist band, and is relevant for calibration matters.</p><p>A convex optimization reduction-based method of peaks-to-average ratio of orthogonal frequency division multiplexing signals is presented and experimentally validated for a wireless local area network system. Improvements on the radio frequency power amplifier level are investigated with respect to power added efficiency, output power, in-band and out-of-band errors. The influence of the power distribution in the excitation signal on power amplifier performance was evaluated.</p>

This thesis presents a continuous time bandpass delta sigma modulator with frequency translation inside the delta sigma loop. The input IF signal is down converted to baseband after amplification by a low Q, wideband bandpass resonator. The down converted IF signal is digitized by a continuous time, second order lowpass delta sigma modulator. The output of the lowpass delta sigma modulator is upconverted and fedback in to the low Q wideband bandpass resonator. Unlike the conventional delta sigma modulators, sinusoidal pulses are used for feedback. The system level design of the frequency translating delta sigma modulator is discussed. A prototype frequency translating delta sigma modulator to digitize IF signals at 100 MHz was designed in CMOS 0.35 μm process. Transistor level simulation shows that 80 dB SNR is achievable at a power dissipation of 100 mW. The frequency translating delta sigma modulator is less sensitive to time delay jitter in the DAC feedback pulse. If we use edge triggered sinusoid pulses for feedback, the DAC jitter performance of frequency translating delta sigma modulator will be better than that of conventional bandpass delta sigma modulator. / Graduation date: 2003

No description available.

This work describes a novel frequency based Current to Digital converter, which would be fully realizable on a single chip. Biological systems make use of delay line techniques to compute many things critical to the life of an animal. Seeking to build up such a system, we are adapting the auditory localization circuit found in barn owls to detect and compute the magnitude of an input current. The increasing drive to produce ultra low-power circuits necessitates the use of very small currents. Frequently these currents need to accurately measured, but current solutions typically involve off-chip measurements. These are usually slow, and moving a current off chip increases noise to the system. Moving a system such as this completely on chip will allow for precise measurement and control of bias currents, and it will allow for better compensation of some common transistor mismatch issues. This project affords an extremely low power (100s nW) converter technology that is also very space efficient. The converter is completely asynchronous which yields ultra-low power standby operation [1].

The multi-service requirements of the 3G and 4G communication systems, and their backward compatibility requirements, create challenges for the antenna and RF front-end designs with multi-band and wide-band techniques. These challenges include: multiple filters, which are lossy, bulky, and expensive, are needed in the system; device board size limitation and the associated isolation problems caused by the limited space and crowd circuits; and the insertion loss issues created by the single-pole-multi-through antenna switch. As will be shown, reconfigurable antennas can perform portions of the filter functions, which can help solve the multiple filters problem. Additionally, reconfigurable RF circuits can decrease the circuit size and output ports, which can help solve board size limitation, and isolation and antenna switch insertion loss issues. To validate the idea that reconfigurable antennas and reconfigurable RF circuits are a viable option for multi-service communication system, a reconfigurable patch antenna, a reconfigurable monopole antenna, and a reconfigurable power amplifier (PA) have been developed. All designs adapt state-of-the-art techniques. For the reconfigurable antenna designs, an experiment demonstrating its advantages, such as jamming signal resistance, has been performed. Reconfigurable antennas provide a better out-ofoperating- band noise performance than the multi-band antennas design, decreasing the need for filters in the system. A full investigation of reconfigurable antennas, including the single service reconfigurable antenna, the mixed signal service reconfigurable antenna, and the multi-band reconfigurable antenna, has been completed. The design challenges, which include switches investigation, switches integration, and service grouping techniques, have been discussed. In the reconfigurable PA portion, a reconfigurable PA structure has first been demonstrated, and includes a reconfigurable output matching network (MN) and a reconfigurable die design. To validate the proposed reconfigurable PA structure, a reconfigurable PA for a 3G cell phone system has been designed with a multi-chip module technique. The reconfigurable PA structure can significantly decrease the real-estate, cost, and complexity of the PA design. Further, by decreasing the number of output ports, the number of poles for the antenna switch will be decreased as well, leading to an insertion loss decrease.